summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorMarek Olšák <[email protected]>2016-05-17 21:25:39 +0200
committerMarek Olšák <[email protected]>2016-06-01 17:35:30 +0200
commit28de7aec0ca98a407ba78fa28934588dec2a5a02 (patch)
treeb79cee6cf8a3aab54dd2b927e57d1509b542e4c3
parent95c5bbae66af3ca1f805d94f6fe8d8e4ba2c9c43 (diff)
radeonsi: move code for setting one shader image into separate function
v2: fix set_shader_images(..., NULL). Found by Christoph Haag. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
-rw-r--r--src/gallium/drivers/radeonsi/si_descriptors.c153
1 files changed, 82 insertions, 71 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index cc296f9d31e..a251fe94b6d 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -505,94 +505,105 @@ si_disable_shader_image(struct si_images_info *images, unsigned slot)
}
}
-static void
-si_set_shader_images(struct pipe_context *pipe, unsigned shader,
- unsigned start_slot, unsigned count,
- struct pipe_image_view *views)
+static void si_set_shader_image(struct si_context *ctx,
+ struct si_images_info *images,
+ unsigned slot, struct pipe_image_view *view)
{
- struct si_context *ctx = (struct si_context *)pipe;
struct si_screen *screen = ctx->screen;
- struct si_images_info *images = &ctx->images[shader];
- unsigned i, slot;
-
- assert(shader < SI_NUM_SHADERS);
+ struct r600_resource *res;
- if (!count)
+ if (!view || !view->resource) {
+ si_disable_shader_image(images, slot);
return;
+ }
- assert(start_slot + count <= SI_NUM_IMAGES);
+ res = (struct r600_resource *)view->resource;
+ util_copy_image_view(&images->views[slot], view);
- for (i = 0, slot = start_slot; i < count; ++i, ++slot) {
- struct r600_resource *res;
+ si_sampler_view_add_buffer(ctx, &res->b.b,
+ RADEON_USAGE_READWRITE);
- if (!views || !views[i].resource) {
- si_disable_shader_image(images, slot);
- continue;
- }
+ if (res->b.b.target == PIPE_BUFFER) {
+ si_make_buffer_descriptor(screen, res,
+ view->format,
+ view->u.buf.first_element,
+ view->u.buf.last_element,
+ images->desc.list + slot * 8);
+ images->compressed_colortex_mask &= ~(1 << slot);
+ } else {
+ static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
+ struct r600_texture *tex = (struct r600_texture *)res;
+ unsigned level;
+ unsigned width, height, depth;
+ uint32_t *desc = images->desc.list + slot * 8;
- res = (struct r600_resource *)views[i].resource;
- util_copy_image_view(&images->views[slot], &views[i]);
+ assert(!tex->is_depth);
+ assert(tex->fmask.size == 0);
- si_sampler_view_add_buffer(ctx, &res->b.b,
- RADEON_USAGE_READWRITE);
+ if (tex->dcc_offset &&
+ view->access & PIPE_IMAGE_ACCESS_WRITE)
+ r600_texture_disable_dcc(&screen->b, tex);
- if (res->b.b.target == PIPE_BUFFER) {
- si_make_buffer_descriptor(screen, res,
- views[i].format,
- views[i].u.buf.first_element,
- views[i].u.buf.last_element,
- images->desc.list + slot * 8);
- images->compressed_colortex_mask &= ~(1 << slot);
+ if (is_compressed_colortex(tex)) {
+ images->compressed_colortex_mask |= 1 << slot;
} else {
- static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
- struct r600_texture *tex = (struct r600_texture *)res;
- unsigned level;
- unsigned width, height, depth;
- uint32_t *desc = images->desc.list + slot * 8;
+ images->compressed_colortex_mask &= ~(1 << slot);
+ }
+
+ if (tex->dcc_offset &&
+ p_atomic_read(&tex->framebuffers_bound))
+ ctx->need_check_render_feedback = true;
+
+ /* Always force the base level to the selected level.
+ *
+ * This is required for 3D textures, where otherwise
+ * selecting a single slice for non-layered bindings
+ * fails. It doesn't hurt the other targets.
+ */
+ level = view->u.tex.level;
+ width = u_minify(res->b.b.width0, level);
+ height = u_minify(res->b.b.height0, level);
+ depth = u_minify(res->b.b.depth0, level);
+
+ si_make_texture_descriptor(screen, tex,
+ false, res->b.b.target,
+ view->format, swizzle,
+ 0, 0,
+ view->u.tex.first_layer,
+ view->u.tex.last_layer,
+ width, height, depth,
+ desc, NULL);
+ si_set_mutable_tex_desc_fields(tex, tex->surface.level, level,
+ util_format_get_blockwidth(view->format),
+ false, desc);
+ }
- assert(!tex->is_depth);
- assert(tex->fmask.size == 0);
+ images->desc.enabled_mask |= 1u << slot;
+ images->desc.dirty_mask |= 1u << slot;
+}
- if (tex->dcc_offset &&
- views[i].access & PIPE_IMAGE_ACCESS_WRITE)
- r600_texture_disable_dcc(&screen->b, tex);
+static void
+si_set_shader_images(struct pipe_context *pipe, unsigned shader,
+ unsigned start_slot, unsigned count,
+ struct pipe_image_view *views)
+{
+ struct si_context *ctx = (struct si_context *)pipe;
+ struct si_images_info *images = &ctx->images[shader];
+ unsigned i, slot;
- if (is_compressed_colortex(tex)) {
- images->compressed_colortex_mask |= 1 << slot;
- } else {
- images->compressed_colortex_mask &= ~(1 << slot);
- }
+ assert(shader < SI_NUM_SHADERS);
- if (tex->dcc_offset &&
- p_atomic_read(&tex->framebuffers_bound))
- ctx->need_check_render_feedback = true;
+ if (!count)
+ return;
- /* Always force the base level to the selected level.
- *
- * This is required for 3D textures, where otherwise
- * selecting a single slice for non-layered bindings
- * fails. It doesn't hurt the other targets.
- */
- level = views[i].u.tex.level;
- width = u_minify(res->b.b.width0, level);
- height = u_minify(res->b.b.height0, level);
- depth = u_minify(res->b.b.depth0, level);
-
- si_make_texture_descriptor(screen, tex,
- false, res->b.b.target,
- views[i].format, swizzle,
- 0, 0,
- views[i].u.tex.first_layer, views[i].u.tex.last_layer,
- width, height, depth,
- desc, NULL);
- si_set_mutable_tex_desc_fields(tex, tex->surface.level,
- level,
- util_format_get_blockwidth(views[i].format),
- false, desc);
- }
+ assert(start_slot + count <= SI_NUM_IMAGES);
- images->desc.enabled_mask |= 1u << slot;
- images->desc.dirty_mask |= 1u << slot;
+ if (views) {
+ for (i = 0, slot = start_slot; i < count; ++i, ++slot)
+ si_set_shader_image(ctx, images, slot, &views[i]);
+ } else {
+ for (i = 0, slot = start_slot; i < count; ++i, ++slot)
+ si_set_shader_image(ctx, images, slot, NULL);
}
}