diff options
| author | Marek Olšák <[email protected]> | 2016-10-23 21:28:29 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-10-26 13:02:58 +0200 |
| commit | 2664351dfeeba2c1d0de272cdf6d5fd940a367e9 (patch) | |
| tree | e85828e3b1cd4a1687402a11f123d157ee24734e | |
| parent | 2a2e53757796b3fed3119cb033e5cf5144843850 (diff) | |
gallium/radeon: re-order radeon_surf::dcc and htile members
Reviewed-by: Nicolai Hähnle <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_winsys.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index cec1274abee..2330cddf631 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -298,7 +298,12 @@ struct radeon_surf { * changed by the calculator. */ uint64_t surf_size; + uint64_t dcc_size; + uint64_t htile_size; + uint32_t surf_alignment; + uint32_t dcc_alignment; + uint32_t htile_alignment; /* This applies to EG and later. */ unsigned bankw:4; /* max 8 */ @@ -323,11 +328,6 @@ struct radeon_surf { struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVELS]; uint8_t tiling_index[RADEON_SURF_MAX_LEVELS]; uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS]; - - uint64_t dcc_size; - uint32_t dcc_alignment; - uint64_t htile_size; - uint32_t htile_alignment; }; struct radeon_bo_list_item { |