diff options
| author | Ian Romanick <[email protected]> | 2019-04-18 17:48:15 -0700 |
|---|---|---|
| committer | Ian Romanick <[email protected]> | 2019-04-23 17:50:28 -0700 |
| commit | 26391cceaa17d9452f9adcf321aa05731eb50a39 (patch) | |
| tree | 8a8bb0167931d349b9f0de79b1bc9e739282cade | |
| parent | fd1fa9afc770a8da0b99f755da762a469ca6a0f3 (diff) | |
intel/compiler: Lower ffma on Gen4 and Gen5
flrp32 is also a 3-source instruction, but there is another pending
series that handles that for Gen4 and Gen5.
v2: Rebase on "intel/compiler: Don't have sepearate, per-Gen
nir_options"
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
| -rw-r--r-- | src/intel/compiler/brw_compiler.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index f1acf838887..44296083711 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -183,6 +183,10 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo) nir_options->lower_flrp32 = true; } } + + /* Prior to Gen6, there are no three source operations. */ + nir_options->lower_ffma = devinfo->gen < 6; + nir_options->lower_int64_options = int64_options; nir_options->lower_doubles_options = fp64_options; compiler->glsl_compiler_options[i].NirOptions = nir_options; |