diff options
| author | Kenneth Graunke <[email protected]> | 2016-03-29 01:32:52 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2016-04-25 13:13:00 -0700 |
| commit | 21b4bcdd05eabe94feb1a17bbb96f55d26eabe6e (patch) | |
| tree | af81f66295666e029957ab388fde94d57e234856 | |
| parent | e915903c10fed378ad6bdb4b3850e8fe8515158d (diff) | |
i965: Unroll SIMD16 DDY_FINE on Sandybridge.
This fixes 10 dEQP-GLES3 subtests:
dEQP-GLES3.functional.shaders.derivate.dfdy.texture.float_nicest.*.
Matt noticed that our Piglit tests for this use even numbered registers,
while the failing dEQP tests use odd numbered registers. We believe
that it works for even numbered registers, but not otherwise.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index fb9f65c6a37..812a75eceed 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -1138,12 +1138,16 @@ fs_generator::generate_ddy(enum opcode opcode, * * Similar text exists in the g45 PRM. * + * Empirically, compressed align16 instructions using odd register + * numbers don't appear to work on Sandybridge either. + * * On these platforms, if we're building a SIMD16 shader, we need to * manually unroll to a pair of SIMD8 instructions. */ bool unroll_to_simd8 = (dispatch_width == 16 && - (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell))); + (devinfo->gen == 4 || devinfo->gen == 6 || + (devinfo->gen == 7 && !devinfo->is_haswell))); /* produce accurate derivatives */ struct brw_reg src0 = brw_reg(src.file, src.nr, 0, |