diff options
| author | Samuel Pitoiset <[email protected]> | 2019-02-12 09:01:50 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-02-12 17:39:30 +0100 |
| commit | 1b8983c25be19073c02fe9630e949be55f8280fa (patch) | |
| tree | dfd3be5f26d8dc6ac8b7bcb478031e615f2df375 | |
| parent | bd1186572f6924a15ea10cd72a95c6d451016bae (diff) | |
radv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8
This fixes a critical issue.
Cc: <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109575
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 5 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 5 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 3 |
3 files changed, 10 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 989372e48b7..ad0b934ddfc 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1373,7 +1373,7 @@ radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset; - if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) { + if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) { radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0)); radeon_emit(cs, va); radeon_emit(cs, va >> 32); @@ -1535,14 +1535,13 @@ radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c; - if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) { + if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) { radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating)); radeon_emit(cs, va); radeon_emit(cs, va >> 32); radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); radeon_emit(cs, 2); } else { - /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */ radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating)); radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) | COPY_DATA_DST_SEL(COPY_DATA_REG) | diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 0fef92773e1..9509b3db13c 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -369,6 +369,11 @@ radv_physical_device_init(struct radv_physical_device *device, device->dcc_msaa_allowed = (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA); + /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */ + device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 || + (device->rad_info.chip_class >= VI && + device->rad_info.me_fw_feature >= 41); + radv_physical_device_init_mem_types(device); radv_fill_device_extension_table(device, &device->supported_extensions); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 1e38a12a2a7..9ce0724cb9f 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -306,6 +306,9 @@ struct radv_physical_device { /* Whether DCC should be enabled for MSAA textures. */ bool dcc_msaa_allowed; + /* Whether LOAD_CONTEXT_REG packets are supported. */ + bool has_load_ctx_reg_pkt; + /* This is the drivers on-disk cache used as a fallback as opposed to * the pipeline cache defined by apps. */ |