i965: Remove fallthrough for Gen4 cube map layout.

Now that both 2DArray and Cube layouts are taken care of by helper
functions, it's easy to just call the right function for each
generation.  This is a little cleaner than falling through.

This also reworks the comments.  Referencing "Volume 1" of the BSpec
isn't very helpful, since that's only available inside Intel, and it
doesn't even use volume numbers.  Also, "Ironlake...finally" sounds a
bit strange considering that almost all hardware uses the 2D array
approach.  At this point, Gen4 is the only special case.

Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Ian Romanick <[email protected]>

1 files changed, 7 insertions, 9 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 17720578c79..6b3d3e20a32 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -151,17 +151,15 @@ brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
 {
    switch (mt->target) {
    case GL_TEXTURE_CUBE_MAP:
-      if (intel->gen >= 5) {
-	 /* On Ironlake, cube maps are finally represented as just a series of
-	  * MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated by a
-	  * pitch of qpitch rows, where qpitch is defined by the equation given
-	  * in Volume 1 of the BSpec.
-	  */
+      if (intel->gen == 4) {
+         /* Gen4 stores cube maps as 3D textures. */
+         assert(mt->physical_depth0 == 6);
+         brw_miptree_layout_texture_3d(intel, mt);
+      } else {
+         /* All other hardware stores cube maps as 2D arrays. */
 	 brw_miptree_layout_texture_array(intel, mt);
-	 break;
       }
-      assert(mt->physical_depth0 == 6);
-      /* FALLTHROUGH */
+      break;
 
    case GL_TEXTURE_3D:
       brw_miptree_layout_texture_3d(intel, mt);