i965/fs: Set pixel/sample mask for compute shaders atomic ops

For fragment programs, we pull this mask from the payload header. The same
mask doesn't exist for compute shaders, so we set all bits to enabled.

Previously we were setting 0xff to support SIMD8 VS, but with CS we
support SIMD16, and therefore we change this to 0xffff.

Related commits for SIMD8 VS:

commit d9cd982d556be560af3bcbcdaf62b6b93eb934a5
Author: Ben Widawsky <[email protected]>
Date:   Sun Feb 15 20:06:59 2015 -0800
    i965/simd8vs: Fix SIMD8 atomics

commit 4a95be9772a255776309f23180519a4a8560f2dd
Author: Jordan Justen <[email protected]>
Date:   Tue Feb 17 09:57:35 2015 -0800
    i965/simd8vs: Fix SIMD8 atomics (read-only)

Note: this mask is ANDed with the execution mask, so some channels may not end
up issuing the atomic operation.

Signed-off-by: Jordan Justen <[email protected]>
Reviewed-by: Ben Widawsky <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>

1 files changed, 4 insertions, 4 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 4b48f2db0f2..fa7d32cdab2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -3014,9 +3014,9 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
        * mask sent in the header to compute the actual set of channels that execute
        * the atomic operation.
        */
-      assert(stage == MESA_SHADER_VERTEX);
+      assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
       emit(MOV(component(sources[0], 7),
-               brw_imm_ud(0xff)))->force_writemask_all = true;
+               brw_imm_ud(0xffff)))->force_writemask_all = true;
    }
    length++;
 
@@ -3077,9 +3077,9 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
        * mask sent in the header to compute the actual set of channels that execute
        * the atomic operation.
        */
-      assert(stage == MESA_SHADER_VERTEX);
+      assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
       emit(MOV(component(sources[0], 7),
-               brw_imm_ud(0xff)))->force_writemask_all = true;
+               brw_imm_ud(0xffff)))->force_writemask_all = true;
    }
 
    /* Set the surface read offset. */