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authorRob Clark <[email protected]>2019-09-25 10:10:39 -0700
committerRob Clark <[email protected]>2019-10-18 15:08:54 -0700
commit0568761f8e7b9249ec8cffbd7826c24e38bf16d6 (patch)
tree174362a432ebe93bf918d9461264a3ffbfec80cd
parentbc2ccdc45ab6de74d72412244984b4551ece855c (diff)
nir: Add a new ALU nir_op_imul24
Some hardware can do 24b multiply in a single instruction, but not 32b. However in most cases 24b is sufficient for address/offset calculation. Signed-off-by: Rob Clark <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
-rw-r--r--src/compiler/nir/nir_opcodes.py3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py
index b759910cd80..4bb21ea1358 100644
--- a/src/compiler/nir/nir_opcodes.py
+++ b/src/compiler/nir/nir_opcodes.py
@@ -1061,3 +1061,6 @@ dst.x = ((((src0.x & 0xffff0000) >> 16) * (src1.x & 0x0000ffff)) << 16) + src2.x
triop("imad24_ir3", tint32, _2src_commutative,
"(((int32_t)src0 << 8) >> 8) * (((int32_t)src1 << 8) >> 8) + src2")
+# 24b multiply into 32b result (with sign extension)
+binop("imul24", tint32, _2src_commutative + associative,
+ "(((int32_t)src0 << 8) >> 8) * (((int32_t)src1 << 8) >> 8)")