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authorJonas Kulla <nyocurio@gmail.com>2017-06-19 19:46:23 +0200
committerJason Ekstrand <jason.ekstrand@intel.com>2017-06-19 12:05:52 -0700
commita52ee32a9a49b48c51a80b8a35aa26bd583cabb7 (patch)
treebb970f02f76880e3687294a91bf9f8cda60de06d
parent3fc99f12990b65610a037f02071bfcf3220eccb9 (diff)
anv: Fix L3 cache programming on Bay Trail
Valid values for URBAllocation start at 32, so substract that before programming the register. This was missed when porting from the GL driver. Cc: "17.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
-rw-r--r--src/intel/vulkan/genX_cmd_buffer.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 59430a24eb9..0216ea04a80 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -835,7 +835,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
anv_pack_struct(&l3cr2, GENX(L3CNTLREG2),
.SLMEnable = has_slm,
.URBLowBandwidth = urb_low_bw,
- .URBAllocation = cfg->n[GEN_L3P_URB],
+ .URBAllocation = cfg->n[GEN_L3P_URB] - n0_urb,
#if !GEN_IS_HASWELL
.ALLAllocation = cfg->n[GEN_L3P_ALL],
#endif