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authorMarek Olšák <[email protected]>2014-12-08 12:41:37 +0100
committerMarek Olšák <[email protected]>2014-12-10 21:59:37 +0100
commit7991d602f370a1bf7ff5040ea3ee2572ee1c76ca (patch)
treec8a6f0d8bd93c92468d1031daa951fc41639e466
parent834bee42ed45b1f993694c27aedd2f24d77d35f1 (diff)
radeonsi: fix line stippling and provoking vertex state for GS primitives
I'm not sure if GS hw outputs line lists or line strips. Reviewed-by: Michel Dänzer <[email protected]>
-rw-r--r--src/gallium/drivers/radeonsi/si_state_draw.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 195d98118f4..4383da4ad09 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -153,7 +153,9 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx, unsigned mode
{
struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
- /* TODO: this should use the GS output primitive type. */
+ if (sctx->gs_shader)
+ mode = sctx->gs_shader->gs_output_prim;
+
r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
sctx->pa_sc_line_stipple |
S_028A0C_AUTO_RESET_CNTL(mode == PIPE_PRIM_LINES ? 1 :