diff options
author | Jason Ekstrand <[email protected]> | 2018-12-14 18:38:08 -0600 |
---|---|---|
committer | Jason Ekstrand <[email protected]> | 2019-01-08 00:38:30 +0000 |
commit | 34af63fa223f953336ecfdd429b13a8317d10046 (patch) | |
tree | de9e2cddcaa75380f10a9e247a09d3e4bb8e7323 | |
parent | 63b9aa2e257475cdee0a1aafcd57c6f123d6e7e6 (diff) |
anv: Enable the new deref-based UBO/SSBO path
Reviewed-by: Alejandro PiƱeiro <[email protected]>
Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
-rw-r--r-- | src/intel/vulkan/anv_nir_apply_pipeline_layout.c | 20 | ||||
-rw-r--r-- | src/intel/vulkan/anv_pipeline.c | 4 |
2 files changed, 23 insertions, 1 deletions
diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c index 00f0798da35..a0fd226b0a0 100644 --- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c +++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c @@ -185,6 +185,23 @@ lower_res_reindex_intrinsic(nir_intrinsic_instr *intrin, } static void +lower_load_vulkan_descriptor(nir_intrinsic_instr *intrin, + struct apply_pipeline_layout_state *state) +{ + nir_builder *b = &state->builder; + + b->cursor = nir_before_instr(&intrin->instr); + + /* We follow the nir_address_format_vk_index_offset model */ + assert(intrin->src[0].is_ssa); + nir_ssa_def *vec2 = nir_vec2(b, intrin->src[0].ssa, nir_imm_int(b, 0)); + + assert(intrin->dest.is_ssa); + nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(vec2)); + nir_instr_remove(&intrin->instr); +} + +static void lower_image_intrinsic(nir_intrinsic_instr *intrin, struct apply_pipeline_layout_state *state) { @@ -380,6 +397,9 @@ apply_pipeline_layout_block(nir_block *block, case nir_intrinsic_vulkan_resource_reindex: lower_res_reindex_intrinsic(intrin, state); break; + case nir_intrinsic_load_vulkan_descriptor: + lower_load_vulkan_descriptor(intrin, state); + break; case nir_intrinsic_image_deref_load: case nir_intrinsic_image_deref_store: case nir_intrinsic_image_deref_atomic_add: diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 682053d997c..4269e618eba 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -135,7 +135,6 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline, struct spirv_to_nir_options spirv_options = { .lower_workgroup_access_to_offsets = true, - .lower_ubo_ssbo_access_to_offsets = true, .caps = { .float64 = device->instance->physicalDevice.info.gen >= 8, .int64 = device->instance->physicalDevice.info.gen >= 8, @@ -214,6 +213,9 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline, NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_shader_in | nir_var_shader_out | nir_var_system_value); + NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_ubo | nir_var_ssbo, + nir_address_format_vk_index_offset); + if (stage == MESA_SHADER_FRAGMENT) NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable); |