diff options
author | Samuel Pitoiset <[email protected]> | 2018-06-14 13:26:20 +0200 |
---|---|---|
committer | Samuel Pitoiset <[email protected]> | 2018-06-15 15:54:00 +0200 |
commit | 2193a6a828085e0ba63e2b768c2d86a86639831f (patch) | |
tree | c51669e9bd62dbeaf0371df5826810421f163d77 | |
parent | be794fa26bd6c05be60a34b4c2773a75de4c7718 (diff) |
radv: update the fast ds clear values only if the image is bound
It's unnecessary to update the fast depth/stencil clear values
if the fast cleared depth/stencil image isn't currently bound.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
-rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 37 |
1 files changed, 32 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index de4af76ce6c..ad83bc6c6f7 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1171,6 +1171,37 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, ds->pa_su_poly_offset_db_fmt_cntl); } +/** + * Update the fast clear depth/stencil values if the image is bound as a + * depth/stencil buffer. + */ +static void +radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer, + struct radv_image *image, + VkClearDepthStencilValue ds_clear_value) +{ + struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer; + const struct radv_subpass *subpass = cmd_buffer->state.subpass; + struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radv_attachment_info *att; + uint32_t att_idx; + + if (!framebuffer || !subpass) + return; + + att_idx = subpass->depth_stencil_attachment.attachment; + if (att_idx == VK_ATTACHMENT_UNUSED) + return; + + att = &framebuffer->attachments[att_idx]; + if (att->attachment->image != image) + return; + + radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2); + radeon_emit(cs, ds_clear_value.stencil); + radeon_emit(cs, fui(ds_clear_value.depth)); +} + void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, @@ -1203,11 +1234,7 @@ radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer, if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); - radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count); - if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) - radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */ - if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) - radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */ + radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value); /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is * only needed when clearing Z to 0.0. |