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authorMarek Olšák <[email protected]>2016-10-01 00:46:39 +0200
committerMarek Olšák <[email protected]>2016-10-04 16:11:51 +0200
commitf92113c5a1c1e928a2f50c78866f43eff4cd6630 (patch)
tree7f3bcd72f07aceb848b65f97ff279e4b3e76a275
parentca1d1e0e19ac9048533b43c910eba75ceb69a312 (diff)
radeonsi: don't check PIPE_BARRIER_MAPPED_BUFFER
Caches are always flushed at IB boundary. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 443dc37078b..04b57dc5e03 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3414,14 +3414,13 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
if (flags & PIPE_BARRIER_FRAMEBUFFER)
sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
- if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
- PIPE_BARRIER_FRAMEBUFFER |
+ if (flags & (PIPE_BARRIER_FRAMEBUFFER |
PIPE_BARRIER_INDIRECT_BUFFER)) {
/* Not sure if INV_GLOBAL_L2 is the best thing here.
*
* We need to make sure that TC L1 & L2 are written back to
- * memory, because neither CPU accesses nor CB fetches consider
- * TC, but there's no need to invalidate any TC cache lines. */
+ * memory, because CB fetches don't consider TC, but there's
+ * no need to invalidate any TC cache lines. */
sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
}
}