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authorMarek Olšák <[email protected]>2018-01-01 21:03:29 +0100
committerMarek Olšák <[email protected]>2018-01-27 02:09:09 +0100
commite17eb8800f3c4255f55b33af53336bd29dbcfa77 (patch)
treec19ffed8fcff3c87da8994f973b8007622d19832
parent0d62370bbb9a70bc4d493fa8be9ddf73c87d15d9 (diff)
ac: move address space definitions to common code
Reviewed-by: Samuel Pitoiset <[email protected]>
-rw-r--r--src/amd/common/ac_llvm_build.h1
-rw-r--r--src/amd/common/ac_nir_to_llvm.c9
-rw-r--r--src/gallium/drivers/radeonsi/si_shader.c11
3 files changed, 7 insertions, 14 deletions
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index 0a9053ef92c..2ca7a97e76e 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -35,6 +35,7 @@ extern "C" {
#endif
enum {
+ AC_CONST_ADDR_SPACE = 2, /* CONST is the only address space that selects SMEM loads */
AC_LOCAL_ADDR_SPACE = 3,
};
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index bd7d77553e8..92188cfb8e3 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -43,9 +43,6 @@ enum radeon_llvm_calling_convention {
RADEON_LLVM_AMDGPU_HS = 93,
};
-#define CONST_ADDR_SPACE 2
-#define LOCAL_ADDR_SPACE 3
-
#define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
#define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
@@ -361,7 +358,7 @@ create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
{
return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
- CONST_ADDR_SPACE);
+ AC_CONST_ADDR_SPACE);
}
static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
@@ -1082,7 +1079,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
&user_sgpr_idx, 2);
if (ctx->options->supports_spill) {
ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
- LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
+ LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
NULL, 0, AC_FUNC_ATTR_READNONE);
ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
const_array(ctx->ac.v4i32, 16), "");
@@ -5762,7 +5759,7 @@ setup_shared(struct ac_nir_context *ctx,
LLVMAddGlobalInAddressSpace(
ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
variable->name ? variable->name : "",
- LOCAL_ADDR_SPACE);
+ AC_LOCAL_ADDR_SPACE);
_mesa_hash_table_insert(ctx->vars, variable, shared);
}
}
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 787af9bae9a..b75dab7cfbb 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -99,11 +99,6 @@ static void si_build_ps_epilog_function(struct si_shader_context *ctx,
*/
#define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
-enum {
- CONST_ADDR_SPACE = 2,
- LOCAL_ADDR_SPACE = 3,
-};
-
static bool llvm_type_is_64bit(struct si_shader_context *ctx,
LLVMTypeRef type)
{
@@ -2224,7 +2219,7 @@ void si_declare_compute_memory(struct si_shader_context *ctx,
{
struct si_shader_selector *sel = ctx->shader->selector;
- LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
+ LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_LOCAL_ADDR_SPACE);
LLVMValueRef var;
assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
@@ -2234,7 +2229,7 @@ void si_declare_compute_memory(struct si_shader_context *ctx,
var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
LLVMArrayType(ctx->i8, sel->local_size),
"compute_lds",
- LOCAL_ADDR_SPACE);
+ AC_LOCAL_ADDR_SPACE);
LLVMSetAlignment(var, 4);
ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
@@ -3953,7 +3948,7 @@ static void clock_emit(
LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements)
{
return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
- CONST_ADDR_SPACE);
+ AC_CONST_ADDR_SPACE);
}
static void si_llvm_emit_ddxy(