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authorOliver McFadden <[email protected]>2008-02-29 05:48:31 +0000
committerOliver McFadden <[email protected]>2008-03-01 06:33:07 +0000
commitc30cc5904dc61c27ea7a4ebf5928c53bca6a7b1d (patch)
tree3fae3eeb30eafb4fad0e83063e41ecd1051511a7
parent3129d8b512d50335fc5c219b65e36fcaaffcd247 (diff)
r300: Added the PVS_SRC_OPERAND documentation from AMD.
-rw-r--r--src/mesa/drivers/dri/r300/r300_reg.h35
-rw-r--r--src/mesa/drivers/dri/r300/r300_vertprog.h59
2 files changed, 56 insertions, 38 deletions
diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index 041ba85665b..b059c1671dc 100644
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -2543,6 +2543,41 @@ enum {
PVS_DST_ADDR_MODE_0_SHIFT = 31,
};
+/* PVS Source Operand Description */
+
+enum {
+ PVS_SRC_REG_TYPE_MASK = 0x3,
+ PVS_SRC_REG_TYPE_SHIFT = 0,
+ SPARE_0_MASK = 0x1,
+ SPARE_0_SHIFT = 2,
+ PVS_SRC_ABS_XYZW_MASK = 0x1,
+ PVS_SRC_ABS_XYZW_SHIFT = 3,
+ PVS_SRC_ADDR_MODE_0_MASK = 0x1,
+ PVS_SRC_ADDR_MODE_0_SHIFT = 4,
+ PVS_SRC_OFFSET_MASK = 0xff,
+ PVS_SRC_OFFSET_SHIFT = 5,
+ PVS_SRC_SWIZZLE_X_MASK = 0x7,
+ PVS_SRC_SWIZZLE_X_SHIFT = 13,
+ PVS_SRC_SWIZZLE_Y_MASK = 0x7,
+ PVS_SRC_SWIZZLE_Y_SHIFT = 16,
+ PVS_SRC_SWIZZLE_Z_MASK = 0x7,
+ PVS_SRC_SWIZZLE_Z_SHIFT = 19,
+ PVS_SRC_SWIZZLE_W_MASK = 0x7,
+ PVS_SRC_SWIZZLE_W_SHIFT = 22,
+ PVS_SRC_MODIFIER_X_MASK = 0x1,
+ PVS_SRC_MODIFIER_X_SHIFT = 25,
+ PVS_SRC_MODIFIER_Y_MASK = 0x1,
+ PVS_SRC_MODIFIER_Y_SHIFT = 26,
+ PVS_SRC_MODIFIER_Z_MASK = 0x1,
+ PVS_SRC_MODIFIER_Z_SHIFT = 27,
+ PVS_SRC_MODIFIER_W_MASK = 0x1,
+ PVS_SRC_MODIFIER_W_SHIFT = 28,
+ PVS_SRC_ADDR_SEL_MASK = 0x3,
+ PVS_SRC_ADDR_SEL_SHIFT = 29,
+ PVS_SRC_ADDR_MODE_1_MASK = 0x0,
+ PVS_SRC_ADDR_MODE_1_SHIFT = 32,
+};
+
/*\}*/
/* BEGIN: Packet 3 commands */
diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.h b/src/mesa/drivers/dri/r300/r300_vertprog.h
index 61da603371e..984233e2ea4 100644
--- a/src/mesa/drivers/dri/r300/r300_vertprog.h
+++ b/src/mesa/drivers/dri/r300/r300_vertprog.h
@@ -3,20 +3,6 @@
#include "r300_reg.h"
-#define R300_VPI_IN_REG_INDEX_SHIFT 5
- /* GUESS based on fglrx native limits */
-#define R300_VPI_IN_REG_INDEX_MASK (255 << 5)
-
-#define R300_VPI_IN_X_SHIFT 13
-#define R300_VPI_IN_Y_SHIFT 16
-#define R300_VPI_IN_Z_SHIFT 19
-#define R300_VPI_IN_W_SHIFT 22
-
-#define R300_VPI_IN_NEG_X (1 << 25)
-#define R300_VPI_IN_NEG_Y (1 << 26)
-#define R300_VPI_IN_NEG_Z (1 << 27)
-#define R300_VPI_IN_NEG_W (1 << 28)
-
#define PVS_VECTOR_OPCODE(opcode, reg_index, reg_writemask, reg_class) \
(((opcode & PVS_DST_OPCODE_MASK) << PVS_DST_OPCODE_SHIFT) \
| ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT) \
@@ -32,13 +18,13 @@
#define PVS_SOURCE_OPCODE(in_reg_index, comp_x, comp_y, comp_z, comp_w, reg_class, negate) \
- (((in_reg_index) << R300_VPI_IN_REG_INDEX_SHIFT) \
- | ((comp_x) << R300_VPI_IN_X_SHIFT) \
- | ((comp_y) << R300_VPI_IN_Y_SHIFT) \
- | ((comp_z) << R300_VPI_IN_Z_SHIFT) \
- | ((comp_w) << R300_VPI_IN_W_SHIFT) \
- | ((negate) << 25) \
- | ((reg_class)))
+ (((in_reg_index & PVS_SRC_OFFSET_MASK) << PVS_SRC_OFFSET_SHIFT) \
+ | ((comp_x & PVS_SRC_SWIZZLE_X_MASK) << PVS_SRC_SWIZZLE_X_SHIFT) \
+ | ((comp_y & PVS_SRC_SWIZZLE_Y_MASK) << PVS_SRC_SWIZZLE_Y_SHIFT) \
+ | ((comp_z & PVS_SRC_SWIZZLE_Z_MASK) << PVS_SRC_SWIZZLE_Z_SHIFT) \
+ | ((comp_w & PVS_SRC_SWIZZLE_W_MASK) << PVS_SRC_SWIZZLE_W_SHIFT) \
+ | ((negate & 0xf) << PVS_SRC_MODIFIER_X_SHIFT) /* X Y Z W */ \
+ | ((reg_class & PVS_SRC_REG_TYPE_MASK) << PVS_SRC_REG_TYPE_SHIFT))
#if 1
@@ -78,25 +64,22 @@
VP_OUTMASK_##outmask)
#define VP_IN(inclass,inidx) \
- (((inidx) << R300_VPI_IN_REG_INDEX_SHIFT) | \
- (PVS_SRC_REG_##inclass << 0) | \
- (PVS_SRC_SELECT_X << R300_VPI_IN_X_SHIFT) | \
- (PVS_SRC_SELECT_Y << R300_VPI_IN_Y_SHIFT) | \
- (PVS_SRC_SELECT_Z << R300_VPI_IN_Z_SHIFT) | \
- (PVS_SRC_SELECT_W << R300_VPI_IN_W_SHIFT))
+ (((inidx & PVS_SRC_OFFSET_MASK) << PVS_SRC_OFFSET_SHIFT) | \
+ ((PVS_SRC_REG_##inclass & PVS_SRC_REG_TYPE_MASK) << PVS_SRC_REG_TYPE_SHIFT) | \
+ ((PVS_SRC_SELECT_X & PVS_SRC_SWIZZLE_X_MASK) << PVS_SRC_SWIZZLE_X_SHIFT) | \
+ ((PVS_SRC_SELECT_Y & PVS_SRC_SWIZZLE_Y_MASK) << PVS_SRC_SWIZZLE_Y_SHIFT) | \
+ ((PVS_SRC_SELECT_Z & PVS_SRC_SWIZZLE_Z_MASK) << PVS_SRC_SWIZZLE_Z_SHIFT) | \
+ ((PVS_SRC_SELECT_W & PVS_SRC_SWIZZLE_W_MASK) << PVS_SRC_SWIZZLE_W_SHIFT))
#define VP_ZERO() \
- ((PVS_SRC_SELECT_FORCE_0 << R300_VPI_IN_X_SHIFT) | \
- (PVS_SRC_SELECT_FORCE_0 << R300_VPI_IN_Y_SHIFT) | \
- (PVS_SRC_SELECT_FORCE_0 << R300_VPI_IN_Z_SHIFT) | \
- (PVS_SRC_SELECT_FORCE_0 << R300_VPI_IN_W_SHIFT))
+ (((PVS_SRC_SELECT_FORCE_0 & PVS_SRC_SWIZZLE_X_MASK) << PVS_SRC_SWIZZLE_X_SHIFT) | \
+ ((PVS_SRC_SELECT_FORCE_0 & PVS_SRC_SWIZZLE_Y_MASK) << PVS_SRC_SWIZZLE_Y_SHIFT) | \
+ ((PVS_SRC_SELECT_FORCE_0 & PVS_SRC_SWIZZLE_Z_MASK) << PVS_SRC_SWIZZLE_Z_SHIFT) | \
+ ((PVS_SRC_SELECT_FORCE_0 & PVS_SRC_SWIZZLE_W_MASK) << PVS_SRC_SWIZZLE_W_SHIFT))
#define VP_ONE() \
- ((PVS_SRC_SELECT_FORCE_1 << R300_VPI_IN_X_SHIFT) | \
- (PVS_SRC_SELECT_FORCE_1 << R300_VPI_IN_Y_SHIFT) | \
- (PVS_SRC_SELECT_FORCE_1 << R300_VPI_IN_Z_SHIFT) | \
- (PVS_SRC_SELECT_FORCE_1 << R300_VPI_IN_W_SHIFT))
-
-#define VP_NEG(in,comp) ((in) ^ (R300_VPI_IN_NEG_##comp))
-#define VP_NEGALL(in,comp) VP_NEG(VP_NEG(VP_NEG(VP_NEG((in),X),Y),Z),W)
+ (((PVS_SRC_SELECT_FORCE_1 & PVS_SRC_SWIZZLE_X_MASK) << PVS_SRC_SWIZZLE_X_SHIFT) | \
+ ((PVS_SRC_SELECT_FORCE_1 & PVS_SRC_SWIZZLE_Y_MASK) << PVS_SRC_SWIZZLE_Y_SHIFT) | \
+ ((PVS_SRC_SELECT_FORCE_1 & PVS_SRC_SWIZZLE_Z_MASK) << PVS_SRC_SWIZZLE_Z_SHIFT) | \
+ ((PVS_SRC_SELECT_FORCE_1 & PVS_SRC_SWIZZLE_W_MASK) << PVS_SRC_SWIZZLE_W_SHIFT))
#endif