diff options
| author | Jason Ekstrand <[email protected]> | 2017-09-06 18:37:34 -0700 |
|---|---|---|
| committer | Emil Velikov <[email protected]> | 2017-11-10 16:29:27 +0000 |
| commit | a44f33f7402915e428b12288cb3df505bc3b8e4e (patch) | |
| tree | 76fd41685d43bb75291f3cb9c30fc03382ace046 | |
| parent | 5cd286710efa56002c4916cabf58a44566313f17 (diff) | |
intel/fs: Don't stomp f0.1 in SIMD16 ballot
In fragment shaders f0.1 is used for discards so doing ballot after a
discard can potentially cause the discard to not happen. However, we
don't support SIMD32 fragment shaders yet so this isn't a problem.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit 6c00240bc650805e0b66aa6e17dbe69bbe41e446)
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 01d91639b35..9d9c238a761 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4211,8 +4211,15 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr case nir_intrinsic_ballot: { const fs_reg value = retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_UD); - const struct brw_reg flag = retype(brw_flag_reg(0, 0), - BRW_REGISTER_TYPE_UD); + struct brw_reg flag = brw_flag_reg(0, 0); + /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well + * as f0.0. This is a problem for fragment programs as we currently use + * f0.1 for discards. Fortunately, we don't support SIMD32 fragment + * programs yet so this isn't a problem. When we do, something will + * have to change. + */ + if (dispatch_width == 32) + flag.type = BRW_REGISTER_TYPE_UD; bld.exec_all().MOV(flag, brw_imm_ud(0u)); bld.CMP(bld.null_reg_ud(), value, brw_imm_ud(0u), BRW_CONDITIONAL_NZ); |