diff options
author | Marek Olšák <[email protected]> | 2012-02-02 10:04:29 +0100 |
---|---|---|
committer | Marek Olšák <[email protected]> | 2012-02-21 21:42:27 +0100 |
commit | 8f5c172c854a52b2a69b8383a55c76f1faa5f704 (patch) | |
tree | 86a1af3fc0e8c9317236e7d40da0031e508062ef | |
parent | 182fd4c54476ced92b61412b0cac5be32e257b53 (diff) |
r600g: consolidate the main draw code
The code was almost the same for r600 and eg. What can't be consolidated is
in the *_prepare functions.
-rw-r--r-- | src/gallium/drivers/r600/evergreen_hw_context.c | 55 | ||||
-rw-r--r-- | src/gallium/drivers/r600/r600.h | 15 | ||||
-rw-r--r-- | src/gallium/drivers/r600/r600_hw_context.c | 57 | ||||
-rw-r--r-- | src/gallium/drivers/r600/r600_state_common.c | 56 |
4 files changed, 50 insertions, 133 deletions
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c index 5d56cfb8f90..f3b207bb75b 100644 --- a/src/gallium/drivers/r600/evergreen_hw_context.c +++ b/src/gallium/drivers/r600/evergreen_hw_context.c @@ -981,59 +981,22 @@ void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struc evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, id); } - -void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw) +/* XXX make a proper state object (atom or pipe_state) out of this */ +void evergreen_context_draw_prepare(struct r600_context *ctx) { + struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)ctx->states[R600_PIPE_STATE_DSA]; struct radeon_winsys_cs *cs = ctx->cs; - unsigned ndwords = 7; - uint32_t *pm4; - uint64_t va; - - if (draw->indices) { - ndwords = 11; - } - if (ctx->num_cs_dw_queries_suspend) - ndwords += 6; - - /* when increasing ndwords, bump the max limit too */ - assert(ndwords <= R600_MAX_DRAW_CS_DWORDS); /* queries need some special values * (this is non-zero if any query is active) */ if (ctx->num_cs_dw_queries_suspend) { - pm4 = &cs->buf[cs->cdw]; - pm4[0] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); - pm4[1] = (R_028004_DB_COUNT_CONTROL - EVERGREEN_CONTEXT_REG_OFFSET) >> 2; - pm4[2] = S_028004_PERFECT_ZPASS_COUNTS(1); - pm4[3] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); - pm4[4] = (R_02800C_DB_RENDER_OVERRIDE - EVERGREEN_CONTEXT_REG_OFFSET) >> 2; - pm4[5] = draw->db_render_override | S_02800C_NOOP_CULL_DISABLE(1); - cs->cdw += 6; - ndwords -= 6; - } - - /* draw packet */ - pm4 = &cs->buf[cs->cdw]; - pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing); - pm4[1] = draw->vgt_index_type; - pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing); - pm4[3] = draw->vgt_num_instances; - if (draw->indices) { - va = r600_resource_va(&ctx->screen->screen, (void*)draw->indices); - va += draw->indices_bo_offset; - pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing); - pm4[5] = va; - pm4[6] = (va >> 32UL) & 0xFF; - pm4[7] = draw->vgt_num_indices; - pm4[8] = draw->vgt_draw_initiator; - pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing); - pm4[10] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ); - } else { - pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing); - pm4[5] = draw->vgt_num_indices; - pm4[6] = draw->vgt_draw_initiator; + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); + cs->buf[cs->cdw++] = (R_028004_DB_COUNT_CONTROL - EVERGREEN_CONTEXT_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = S_028004_PERFECT_ZPASS_COUNTS(1); + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); + cs->buf[cs->cdw++] = (R_02800C_DB_RENDER_OVERRIDE - EVERGREEN_CONTEXT_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = dsa->db_render_override | S_02800C_NOOP_CULL_DISABLE(1); } - cs->cdw += ndwords; } void evergreen_flush_vgt_streamout(struct r600_context *ctx) diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h index 229fa7068b2..1bb6c4bdee4 100644 --- a/src/gallium/drivers/r600/r600.h +++ b/src/gallium/drivers/r600/r600.h @@ -195,17 +195,6 @@ struct r600_so_target { #define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1) #define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2) -struct r600_draw { - uint32_t vgt_num_indices; - uint32_t vgt_num_instances; - uint32_t vgt_index_type; - uint32_t vgt_draw_initiator; - uint32_t indices_bo_offset; - unsigned db_render_override; - unsigned db_render_control; - struct r600_resource *indices; -}; - struct r600_context; struct r600_screen; @@ -219,7 +208,7 @@ void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r6 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); void r600_context_flush(struct r600_context *ctx, unsigned flags); -void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw); +void r600_context_draw_prepare(struct r600_context *ctx); struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type); void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query); @@ -247,7 +236,7 @@ void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block * void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block); int evergreen_context_init(struct r600_context *ctx); -void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw); +void evergreen_context_draw_prepare(struct r600_context *ctx); void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index 6e3b809cb91..3632c6d14c2 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -1233,63 +1233,24 @@ void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r60 LIST_DELINIT(&block->list); } -void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw) +/* XXX make a proper state object (atom or pipe_state) out of this */ +void r600_context_draw_prepare(struct r600_context *ctx) { + struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)ctx->states[R600_PIPE_STATE_DSA]; struct radeon_winsys_cs *cs = ctx->cs; - unsigned ndwords = 7; - uint32_t *pm4; - - if (draw->indices) { - ndwords = 11; - } - if (ctx->num_cs_dw_queries_suspend) { - if (ctx->family >= CHIP_RV770) - ndwords += 3; - ndwords += 3; - } - - /* when increasing ndwords, bump the max limit too */ - assert(ndwords <= R600_MAX_DRAW_CS_DWORDS); /* queries need some special values * (this is non-zero if any query is active) */ if (ctx->num_cs_dw_queries_suspend) { if (ctx->family >= CHIP_RV770) { - pm4 = &cs->buf[cs->cdw]; - pm4[0] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); - pm4[1] = (R_028D0C_DB_RENDER_CONTROL - R600_CONTEXT_REG_OFFSET) >> 2; - pm4[2] = draw->db_render_control | S_028D0C_R700_PERFECT_ZPASS_COUNTS(1); - cs->cdw += 3; - ndwords -= 3; + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); + cs->buf[cs->cdw++] = (R_028D0C_DB_RENDER_CONTROL - R600_CONTEXT_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = dsa->db_render_control | S_028D0C_R700_PERFECT_ZPASS_COUNTS(1); } - pm4 = &cs->buf[cs->cdw]; - pm4[0] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); - pm4[1] = (R_028D10_DB_RENDER_OVERRIDE - R600_CONTEXT_REG_OFFSET) >> 2; - pm4[2] = draw->db_render_override | S_028D10_NOOP_CULL_DISABLE(1); - cs->cdw += 3; - ndwords -= 3; - } - - /* draw packet */ - pm4 = &cs->buf[cs->cdw]; - pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing); - pm4[1] = draw->vgt_index_type; - pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing); - pm4[3] = draw->vgt_num_instances; - if (draw->indices) { - pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing); - pm4[5] = draw->indices_bo_offset; - pm4[6] = 0; - pm4[7] = draw->vgt_num_indices; - pm4[8] = draw->vgt_draw_initiator; - pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing); - pm4[10] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ); - } else { - pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing); - pm4[5] = draw->vgt_num_indices; - pm4[6] = draw->vgt_draw_initiator; + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); + cs->buf[cs->cdw++] = (R_028D10_DB_RENDER_OVERRIDE - R600_CONTEXT_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = dsa->db_render_override | S_028D10_NOOP_CULL_DISABLE(1); } - cs->cdw += ndwords; } void r600_inval_shader_cache(struct r600_context *ctx) diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index c0f57b995ba..e2a28020cd4 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -33,6 +33,7 @@ #include "r600_formats.h" #include "r600_pipe.h" #include "r600d.h" +#include "r600_hw_context_priv.h" static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom) { @@ -779,13 +780,13 @@ static void r600_update_derived_state(struct r600_context *rctx) void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) { struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA]; struct pipe_draw_info info = *dinfo; - struct r600_draw rdraw = {}; struct pipe_index_buffer ib = {}; unsigned prim, mask, ls_mask = 0; struct r600_block *dirty_block = NULL, *next_block = NULL; struct r600_atom *state = NULL, *next_state = NULL; + struct radeon_winsys_cs *cs = rctx->cs; + uint64_t va; if ((!info.count && (info.indexed || !info.count_from_stream_output)) || (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) || @@ -801,9 +802,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) u_vbuf_draw_begin(rctx->vbuf_mgr, &info); r600_vertex_buffer_update(rctx); - rdraw.vgt_num_indices = info.count; - rdraw.vgt_num_instances = info.instance_count; - if (info.indexed) { /* Initialize the index buffer struct. */ pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer); @@ -816,24 +814,9 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) if (u_vbuf_resource(ib.buffer)->user_ptr) { r600_upload_index_buffer(rctx, &ib, info.count); } - - /* Initialize the r600_draw struct with index buffer info. */ - if (ib.index_size == 4) { - rdraw.vgt_index_type = VGT_INDEX_32 | - (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0); - } else { - rdraw.vgt_index_type = VGT_INDEX_16 | - (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0); - } - rdraw.indices = (struct r600_resource*)ib.buffer; - rdraw.indices_bo_offset = ib.offset; - rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA; } else { info.index_bias = info.start; - rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX; if (info.count_from_stream_output) { - rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1); - r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output); } } @@ -882,10 +865,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) r600_context_pipe_state_set(rctx, &rctx->vgt); - rdraw.db_render_override = dsa->db_render_override; - rdraw.db_render_control = dsa->db_render_control; - - /* Emit states. */ + /* Emit states (the function expects that we emit at most 17 dwords here). */ r600_need_cs_space(rctx, 0, TRUE); LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) { @@ -906,9 +886,33 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) } if (rctx->chip_class >= EVERGREEN) { - evergreen_context_draw(rctx, &rdraw); + evergreen_context_draw_prepare(rctx); + } else { + r600_context_draw_prepare(rctx); + } + + /* draw packet */ + cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing); + cs->buf[cs->cdw++] = ib.index_size == 4 ? + (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) : + (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0)); + cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing); + cs->buf[cs->cdw++] = info.instance_count; + if (info.indexed) { + va = r600_resource_va(ctx->screen, ib.buffer); + va += ib.offset; + cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing); + cs->buf[cs->cdw++] = va; + cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; + cs->buf[cs->cdw++] = info.count; + cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA; + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing); + cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ); } else { - r600_context_draw(rctx, &rdraw); + cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing); + cs->buf[cs->cdw++] = info.count; + cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX | + (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0); } rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING; |