diff options
| author | Jason Ekstrand <[email protected]> | 2017-09-06 20:32:30 -0700 |
|---|---|---|
| committer | Emil Velikov <[email protected]> | 2017-11-10 16:29:27 +0000 |
| commit | 7db7159536569ff965b3a4b6e2e7181462d3a369 (patch) | |
| tree | 24ad60e11622b78174b13dd1aca4250f144119f8 | |
| parent | a44f33f7402915e428b12288cb3df505bc3b8e4e (diff) | |
intel/fs: Use an explicit D type for vote any/all/eq intrinsics
The any/all intrinsics return a boolean value so D or UD is the correct
type. Unfortunately, get_nir_dest has the annoying behavior of
returnning a float type by default. This causes format conversion which
gives us -1.0f or 0.0f in the register. If the consumer of the result
does an integer comparison to zero, it will give you the right boolean
value but if we do something more clever based on the 0/~0 assumption
for booleans, this will give the wrong value.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit 1f416630079f38110910ba796f70e2b81e9ddbf4)
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 9d9c238a761..1213a10b377 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4154,6 +4154,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0)); } bld.CMP(bld.null_reg_d(), get_nir_src(instr->src[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ); + + dest.type = BRW_REGISTER_TYPE_D; bld.MOV(dest, brw_imm_d(-1)); set_predicate(dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ANY8H : dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ANY16H : @@ -4176,6 +4178,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff)); } bld.CMP(bld.null_reg_d(), get_nir_src(instr->src[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ); + + dest.type = BRW_REGISTER_TYPE_D; bld.MOV(dest, brw_imm_d(-1)); set_predicate(dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ALL8H : dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ALL16H : @@ -4200,6 +4204,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff)); } bld.CMP(bld.null_reg_d(), value, uniformized, BRW_CONDITIONAL_Z); + + dest.type = BRW_REGISTER_TYPE_D; bld.MOV(dest, brw_imm_d(-1)); set_predicate(dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ALL8H : dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ALL16H : |