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authorEric Anholt <[email protected]>2012-05-23 09:51:33 -0700
committerEric Anholt <[email protected]>2012-05-23 10:39:45 -0700
commit5b248e598293e7c21257d35904294da4c8f2da58 (patch)
tree3af9e40d3fbb12028fbf51aa0d2ec6b62214490d
parent39a91be20d0592af4f93458364d027b7ade6b2ba (diff)
i965/gen6: Add CC viewport state setup to blorp code.
While it doesn't have the same warning in the simulator as in gen7, let's emit it out of paranoia. We wouldn't want our resolves of some previous clear to get clamped to some current clamping value. Suggested-by: pretty much everyone
-rw-r--r--src/mesa/drivers/dri/i965/gen6_blorp.cpp26
1 files changed, 26 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 7b3bdf31d9d..11bd72ed99f 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -961,6 +961,31 @@ gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
ADVANCE_BATCH();
}
+/* 3DSTATE_VIEWPORT_STATE_POINTERS */
+void
+gen6_blorp_emit_viewport_state(struct brw_context *brw,
+ const brw_blorp_params *params)
+{
+ struct intel_context *intel = &brw->intel;
+ struct brw_cc_viewport *ccv;
+ uint32_t cc_vp_offset;
+
+ ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
+ sizeof(*ccv), 32,
+ &cc_vp_offset);
+
+ ccv->min_depth = 0.0;
+ ccv->max_depth = 1.0;
+
+ BEGIN_BATCH(4);
+ OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS << 16 | (4 - 2) |
+ GEN6_CC_VIEWPORT_MODIFY);
+ OUT_BATCH(0); /* clip VP */
+ OUT_BATCH(0); /* SF VP */
+ OUT_BATCH(cc_vp_offset);
+ ADVANCE_BATCH();
+}
+
/* 3DPRIMITIVE */
static void
@@ -1043,6 +1068,7 @@ gen6_blorp_exec(struct intel_context *intel,
gen6_blorp_emit_wm_config(brw, params, prog_offset, prog_data);
if (params->use_wm_prog)
gen6_blorp_emit_binding_table_pointers(brw, params, wm_bind_bo_offset);
+ gen6_blorp_emit_viewport_state(brw, params);
if (params->depth.mt)
gen6_blorp_emit_depth_stencil_config(brw, params);