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authorIlia Mirkin <[email protected]>2014-04-17 20:16:02 -0400
committerIlia Mirkin <[email protected]>2014-04-19 13:23:32 -0400
commit2d2e60bdeeee19798c9828b543ffb1aca3270325 (patch)
treef36f82d3b69ee06b220646957e50c691a3ca11a9
parentb45f65e760892562966f9ddd2d51a29887e5740d (diff)
gallium/docs: fix PIPE_CAP_ENDIANNESS delimiter, remove trailing spaces
Signed-off-by: Ilia Mirkin <[email protected]>
-rw-r--r--src/gallium/docs/source/screen.rst8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst
index 5c255d05cc5..89cbdbf8051 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -168,8 +168,8 @@ The integer capabilities:
* ``PIPE_CAP_MAX_VIEWPORTS``: The maximum number of viewports (and scissors
since they are linked) a driver can support. Returning 0 is equivalent
to returning 1 because every driver has to support at least a single
- viewport/scissor combination.
-* ''PIPE_CAP_ENDIANNESS``:: The endianness of the device. Either
+ viewport/scissor combination.
+* ``PIPE_CAP_ENDIANNESS``:: The endianness of the device. Either
PIPE_ENDIAN_BIG or PIPE_ENDIAN_LITTLE.
* ``PIPE_CAP_MIXED_FRAMEBUFFER_SIZES``: Whether it is allowed to have
different sizes for fb color/zs attachments. This controls whether
@@ -239,7 +239,7 @@ support different features.
to any shader stage using ``set_constant_buffer``. If 0 or 1, the pipe will
only permit binding one constant buffer per shader, and the shaders will
not permit two-dimensional access to constants.
-
+
If a value greater than 0 is returned, the driver can have multiple
constant buffers bound to shader stages. The CONST register file can
be accessed with two-dimensional indices, like in the example below.
@@ -251,7 +251,7 @@ MOV OUT[0], CONST[0][3] # copy vector 3 of constbuf 0
For backwards compatibility, one-dimensional access to CONST register
file is still supported. In that case, the constbuf index is assumed
to be 0.
-
+
* ``PIPE_SHADER_CAP_MAX_TEMPS``: The maximum number of temporary registers.
* ``PIPE_SHADER_CAP_MAX_ADDRS``: The maximum number of address registers.
* ``PIPE_SHADER_CAP_MAX_PREDS``: The maximum number of predicate registers.