diff options
| author | Henri Verbeet <[email protected]> | 2011-03-14 22:07:44 +0100 |
|---|---|---|
| committer | Henri Verbeet <[email protected]> | 2011-03-14 22:15:56 +0100 |
| commit | 1a8dc1539b59ab61a6f81a4de32b69978dded7ff (patch) | |
| tree | dd84647387f7db3506703feaf598d5d454455938 | |
| parent | ab1a2e454eaeb798b7c4b782877f58266ebab3a1 (diff) | |
r600g: Properly update MULTIWRITE_ENABLE in r600_pipe_shader_ps().
This sort of worked because blend state setup cleared MULTIWRITE_ENABLE again,
but that's not something we want to depend on.
Signed-off-by: Henri Verbeet <[email protected]>
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_state.c | 14 |
2 files changed, 7 insertions, 8 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index fedca3baad5..77432661b64 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1438,6 +1438,7 @@ void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader r600_pipe_state_add_reg(rstate, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps, 0xFFFFFFFF, NULL); + /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */ /* only set some bits here, the other bits are set in the dsa state */ r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 2afa37443fd..7378b30c2eb 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -152,8 +152,9 @@ static void *r600_create_blend_state(struct pipe_context *ctx, } } blend->cb_target_mask = target_mask; + /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */ r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL, - color_control, 0xFFFFFFFF, NULL); + color_control, 0xFFFFFFFD, NULL); for (int i = 0; i < 8; i++) { unsigned eqRGB = state->rt[i].rgb_func; @@ -1297,13 +1298,10 @@ void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shad r600_pipe_state_add_reg(rstate, R_0288CC_SQ_PGM_CF_OFFSET_PS, 0x00000000, 0xFFFFFFFF, NULL); - - if (rshader->fs_write_all) { - r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL, - S_028808_MULTIWRITE_ENABLE(1), - S_028808_MULTIWRITE_ENABLE(1), - NULL); - } + r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL, + S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all), + S_028808_MULTIWRITE_ENABLE(1), + NULL); /* only set some bits here, the other bits are set in the dsa state */ r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, |