diff options
| author | Jason Ekstrand <[email protected]> | 2016-04-15 09:53:42 -0700 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2016-04-15 09:53:55 -0700 |
| commit | c3362453f9235251253daefbb46c40e1cb07a790 (patch) | |
| tree | 522c37da6df28bd37a218662e8f2f95b8e925bf6 | |
| parent | 76fa7b16f474253356d3bf59adc91769dc51f184 (diff) | |
Revert "i965/fs: Feel free to spill partial reads/writes"
This reverts commit 2434ceabf41e66f2a3627ea8591e5ca427a78cce.
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index 8396854fcb1..791da0e038e 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp @@ -808,13 +808,30 @@ fs_visitor::choose_spill_reg(struct ra_graph *g) */ foreach_block_and_inst(block, fs_inst, inst, cfg) { for (unsigned int i = 0; i < inst->sources; i++) { - if (inst->src[i].file == VGRF) + if (inst->src[i].file == VGRF) { spill_costs[inst->src[i].nr] += loop_scale; + + /* Register spilling logic assumes full-width registers; smeared + * registers have a width of 1 so if we try to spill them we'll + * generate invalid assembly. This shouldn't be a problem because + * smeared registers are only used as short-term temporaries when + * loading pull constants, so spilling them is unlikely to reduce + * register pressure anyhow. + */ + if (!inst->src[i].is_contiguous()) { + no_spill[inst->src[i].nr] = true; + } + } } - if (inst->dst.file == VGRF) + if (inst->dst.file == VGRF) { spill_costs[inst->dst.nr] += inst->regs_written * loop_scale; + if (!inst->dst.is_contiguous()) { + no_spill[inst->dst.nr] = true; + } + } + switch (inst->opcode) { case BRW_OPCODE_DO: |