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authorJason Ekstrand <[email protected]>2017-06-05 11:49:24 -0700
committerJason Ekstrand <[email protected]>2017-06-07 08:54:54 -0700
commitacb9a2ef8f5d92002ed7eb7676c4a96db661ba3a (patch)
tree52f265974321dfdb122c9f9bfc1703b28f0c584f
parent252b004a51d951391846ec5644abe88bfffb72bd (diff)
i965: Move the pre-depth-clear flush/stalls to intel_hiz_exec
Cc: "17.1" <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.c58
-rw-r--r--src/mesa/drivers/dri/i965/brw_clear.c56
2 files changed, 58 insertions, 56 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 0d1ccd371f8..1e4c0de5e6b 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1030,6 +1030,49 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
DBG("%s %s to mt %p level %d layers %d-%d\n",
__func__, opname, mt, level, start_layer, start_layer + num_layers - 1);
+ if (op == BLORP_HIZ_OP_DEPTH_CLEAR) {
+ if (brw->gen == 6) {
+ /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
+ *
+ * "If other rendering operations have preceded this clear, a
+ * PIPE_CONTROL with write cache flush enabled and Z-inhibit
+ * disabled must be issued before the rectangle primitive used for
+ * the depth buffer clear operation.
+ */
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_RENDER_TARGET_FLUSH |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ PIPE_CONTROL_CS_STALL);
+ } else if (brw->gen >= 7) {
+ /*
+ * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
+ *
+ * If other rendering operations have preceded this clear, a
+ * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
+ * enabled must be issued before the rectangle primitive used for
+ * the depth buffer clear operation.
+ *
+ * Same applies for Gen8 and Gen9.
+ *
+ * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
+ * PIPE_CONTROL, Depth Cache Flush Enable:
+ *
+ * This bit must not be set when Depth Stall Enable bit is set in
+ * this packet.
+ *
+ * This is confirmed to hold for real, HSW gets immediate gpu hangs.
+ *
+ * Therefore issue two pipe control flushes, one for cache flush and
+ * another for depth stall.
+ */
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ PIPE_CONTROL_CS_STALL);
+
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
+ }
+ }
+
if (brw->gen >= 8) {
for (unsigned a = 0; a < num_layers; a++)
gen8_hiz_exec(brw, mt, level, start_layer + a, op);
@@ -1037,4 +1080,19 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
for (unsigned a = 0; a < num_layers; a++)
gen6_blorp_hiz_exec(brw, mt, level, start_layer + a, op);
}
+
+ if (brw->gen == 6 && op == BLORP_HIZ_OP_DEPTH_CLEAR) {
+ /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
+ *
+ * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be followed
+ * by a PIPE_CONTROL command with DEPTH_STALL bit set and Then
+ * followed by Depth FLUSH'
+ */
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_DEPTH_STALL);
+
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ PIPE_CONTROL_CS_STALL);
+ }
}
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index f42ea3860e3..ad0d9770ec2 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -166,47 +166,6 @@ brw_fast_clear_depth(struct gl_context *ctx)
mt->fast_clear_color.f32[0] = ctx->Depth.Clear;
}
- if (brw->gen == 6) {
- /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
- *
- * "If other rendering operations have preceded this clear, a
- * PIPE_CONTROL with write cache flush enabled and Z-inhibit disabled
- * must be issued before the rectangle primitive used for the depth
- * buffer clear operation.
- */
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_RENDER_TARGET_FLUSH |
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_CS_STALL);
- } else if (brw->gen >= 7) {
- /*
- * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
- *
- * If other rendering operations have preceded this clear, a
- * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
- * enabled must be issued before the rectangle primitive used for the
- * depth buffer clear operation.
- *
- * Same applies for Gen8 and Gen9.
- *
- * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1 PIPE_CONTROL,
- * Depth Cache Flush Enable:
- *
- * This bit must not be set when Depth Stall Enable bit is set in
- * this packet.
- *
- * This is confirmed to hold for real, HSW gets immediate gpu hangs.
- *
- * Therefore issue two pipe control flushes, one for cache flush and
- * another for depth stall.
- */
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_CS_STALL);
-
- brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
- }
-
if (fb->MaxNumLayers > 0) {
intel_hiz_exec(brw, mt, depth_irb->mt_level,
depth_irb->mt_layer, depth_irb->layer_count,
@@ -216,21 +175,6 @@ brw_fast_clear_depth(struct gl_context *ctx)
BLORP_HIZ_OP_DEPTH_CLEAR);
}
- if (brw->gen == 6) {
- /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
- *
- * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be followed
- * by a PIPE_CONTROL command with DEPTH_STALL bit set and Then
- * followed by Depth FLUSH'
- */
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_DEPTH_STALL);
-
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_CS_STALL);
- }
-
/* Now, the HiZ buffer contains data that needs to be resolved to the depth
* buffer.
*/