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authorEric Anholt <[email protected]>2011-06-19 11:33:40 -0700
committerEric Anholt <[email protected]>2011-06-28 10:17:39 -0700
commitcd7bfd5d44f543246faa7ad6ff2f8309189be963 (patch)
tree678f429b366a80ffa46ed5ba61493fe8776b0628
parent6479922499638b81569db20394c6cb59e6baf989 (diff)
i965/gen6: Fix scissors using invalid STATE_BASE_ADDRESS.
The scissor state was incorrectly in a .prepare function instead of .emit, so the packet would end up in the batch before the STATE_BASE_ADDRESS. It appears that this doesn't actually hurt, as the scissor address gets dereferenced according to the current SBA at draw time.
-rw-r--r--src/mesa/drivers/dri/i965/gen6_scissor_state.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_scissor_state.c b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
index fad3ca0dd04..7492e508864 100644
--- a/src/mesa/drivers/dri/i965/gen6_scissor_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
@@ -31,7 +31,7 @@
#include "intel_batchbuffer.h"
static void
-gen6_prepare_scissor_state(struct brw_context *brw)
+gen6_upload_scissor_state(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
struct gl_context *ctx = &intel->ctx;
@@ -89,5 +89,5 @@ const struct brw_tracked_state gen6_scissor_state = {
.brw = BRW_NEW_BATCH,
.cache = 0,
},
- .prepare = gen6_prepare_scissor_state,
+ .emit = gen6_upload_scissor_state,
};