i965/blorp: Allow blend state to be set for multiple render targets

Original blorp writes only one buffer per shader invocation. Once
the launch mechanism is shared with glsl-based programs there will
be need for supporting multiple render targets.

Also drop the always constant color write disable settings.

Reviewed-by: Kenneth Graunke <[email protected]>
Signed-off-by: Topi Pohjolainen <[email protected]>

3 files changed, 18 insertions, 19 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 0c0cd2bc9f9..8f82851a624 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -155,7 +155,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
 }
 
 
-brw_blorp_params::brw_blorp_params(unsigned num_varyings)
+brw_blorp_params::brw_blorp_params(unsigned num_varyings,
+                                   unsigned num_draw_buffers)
    : x0(0),
      y0(0),
      x1(0),
@@ -163,12 +164,9 @@ brw_blorp_params::brw_blorp_params(unsigned num_varyings)
      depth_format(0),
      hiz_op(GEN6_HIZ_OP_NONE),
      use_wm_prog(false),
-     num_varyings(num_varyings)
+     num_varyings(num_varyings),
+     num_draw_buffers(num_draw_buffers)
 {
-   color_write_disable[0] = false;
-   color_write_disable[1] = false;
-   color_write_disable[2] = false;
-   color_write_disable[3] = false;
 }
 
 extern "C" {
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index 0ba3891c298..c9957a6a8e5 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -211,7 +211,8 @@ struct brw_blorp_prog_data
 class brw_blorp_params
 {
 public:
-   explicit brw_blorp_params(unsigned num_varyings = 0);
+   brw_blorp_params(unsigned num_varyings = 0,
+                    unsigned num_draw_buffers = 1);
 
    virtual uint32_t get_wm_prog(struct brw_context *brw,
                                 brw_blorp_prog_data **prog_data) const = 0;
@@ -227,8 +228,8 @@ public:
    enum gen6_hiz_op hiz_op;
    bool use_wm_prog;
    brw_blorp_wm_push_constants wm_push_consts;
-   bool color_write_disable[4];
    const unsigned num_varyings;
+   const unsigned num_draw_buffers;
 };
 
 
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 405a3e8967d..bfd20016d63 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -246,21 +246,21 @@ gen6_blorp_emit_blend_state(struct brw_context *brw,
 {
    uint32_t cc_blend_state_offset;
 
+   assume(params->num_draw_buffers);
+
+   const unsigned size = params->num_draw_buffers *
+                         sizeof(struct gen6_blend_state);
    struct gen6_blend_state *blend = (struct gen6_blend_state *)
-      brw_state_batch(brw, AUB_TRACE_BLEND_STATE,
-                      sizeof(struct gen6_blend_state), 64,
+      brw_state_batch(brw, AUB_TRACE_BLEND_STATE, size, 64,
                       &cc_blend_state_offset);
 
-   memset(blend, 0, sizeof(*blend));
-
-   blend->blend1.pre_blend_clamp_enable = 1;
-   blend->blend1.post_blend_clamp_enable = 1;
-   blend->blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT;
+   memset(blend, 0, size);
 
-   blend->blend1.write_disable_r = params->color_write_disable[0];
-   blend->blend1.write_disable_g = params->color_write_disable[1];
-   blend->blend1.write_disable_b = params->color_write_disable[2];
-   blend->blend1.write_disable_a = params->color_write_disable[3];
+   for (unsigned i = 0; i < params->num_draw_buffers; ++i) {
+      blend[i].blend1.pre_blend_clamp_enable = 1;
+      blend[i].blend1.post_blend_clamp_enable = 1;
+      blend[i].blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT;
+   }
 
    return cc_blend_state_offset;
 }