diff options
author | Francisco Jerez <[email protected]> | 2015-02-09 21:04:53 +0200 |
---|---|---|
committer | Francisco Jerez <[email protected]> | 2015-08-11 15:07:39 +0300 |
commit | 786e0853bebc3c4ab073bdbb48eec8ba5ea93842 (patch) | |
tree | d4b2fb2cb6a4c742dd3ac9506ba66366700da9ae | |
parent | ac7664e493655e290783c23a0412b9c70936da50 (diff) |
i965/gen7-8: Set up early depth/stencil control appropriately for image load/store.
v2: Store early fragment test mode in brw_wm_prog_data instead of
getting it from core mesa data structures (Ken).
Reviewed-by: Kenneth Graunke <[email protected]>
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.h | 1 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 3 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_state.c | 6 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/gen8_depth_state.c | 6 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/gen8_ps_state.c | 6 |
6 files changed, 21 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 707cd8f9ae5..b52bca77460 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -466,6 +466,7 @@ struct brw_wm_prog_data { uint8_t computed_depth_mode; + bool early_fragment_tests; bool no_8; bool dual_src_blend; bool uses_pos_offset; diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 7fa7c5f06f9..82a36357de9 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -2384,6 +2384,9 @@ enum brw_wm_barycentric_interp_mode { # define GEN7_WM_KILL_ENABLE (1 << 25) # define GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT 23 # define GEN7_WM_USES_SOURCE_DEPTH (1 << 20) +# define GEN7_WM_EARLY_DS_CONTROL_NORMAL (0 << 21) +# define GEN7_WM_EARLY_DS_CONTROL_PSEXEC (1 << 21) +# define GEN7_WM_EARLY_DS_CONTROL_PREPS (2 << 21) # define GEN7_WM_USES_SOURCE_W (1 << 19) # define GEN7_WM_POSITION_ZW_PIXEL (0 << 17) # define GEN7_WM_POSITION_ZW_CENTROID (2 << 17) diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 184f21c7b06..6ee92848172 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -179,6 +179,8 @@ brw_codegen_wm_prog(struct brw_context *brw, fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK); prog_data.computed_depth_mode = computed_depth_mode(&fp->program); + prog_data.early_fragment_tests = fs && fs->EarlyFragmentTests; + /* Use ALT floating point mode for ARB programs so that 0^0 == 1. */ if (!prog) prog_data.base.use_alt_mode = true; diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 285311ef53c..fd6dab5be8b 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -107,6 +107,12 @@ upload_wm_state(struct brw_context *brw) dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK; } + /* BRW_NEW_FS_PROG_DATA */ + if (prog_data->early_fragment_tests) + dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS; + else if (prog_data->base.nr_image_params) + dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC; + /* _NEW_BUFFERS | _NEW_COLOR */ if (brw->is_haswell && !(brw_color_buffer_write_enabled(brw) || writes_depth) && diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c index 8f23702d66b..93100a0708f 100644 --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c @@ -250,10 +250,10 @@ pma_fix_enable(const struct brw_context *brw) */ const bool hiz_enabled = depth_irb && intel_renderbuffer_has_hiz(depth_irb); - /* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2). - * We always leave this set to EDSC_NORMAL (0). + /* BRW_NEW_FS_PROG_DATA: + * 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2). */ - const bool edsc_not_preps = true; + const bool edsc_not_preps = !brw->wm.prog_data->early_fragment_tests; /* 3DSTATE_PS_EXTRA::PixelShaderValid is always true. */ const bool pixel_shader_valid = true; diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c index f84fbe1864d..ae18f0f162c 100644 --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c @@ -119,6 +119,12 @@ upload_wm_state(struct brw_context *brw) dw1 |= brw->wm.prog_data->barycentric_interp_modes << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; + /* BRW_NEW_FS_PROG_DATA */ + if (brw->wm.prog_data->early_fragment_tests) + dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS; + else if (brw->wm.prog_data->base.nr_image_params) + dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC; + BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2)); OUT_BATCH(dw1); |