diff options
author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2016-05-21 16:28:09 +0200 |
---|---|---|
committer | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2016-05-21 16:50:28 +0200 |
commit | e7d2ef42a5a93789990922b4624096d7ce537cb7 (patch) | |
tree | 5404fc159045788b0c45ea2b8982c80332ee0b4c | |
parent | 5e32cc91921209ed27027c57d6bff3d25e189e5a (diff) |
nvc0/ir: don't check the format for surface stores on Kepler
Initially to make sure the format doesn't mismatch and won't produce
out-of-bounds access, we checked that both formats have exactly the same
number of bytes, but this should not be checked for type stores.
This fixes serious rendering issues in the UE4 demos (tested with
realistic and reflections).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
-rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 0a3964c3b04..43a6e5f0fb1 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -1834,18 +1834,17 @@ NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction *su) TYPE_U32, bld.mkImm(0), loadSuInfo32(ind, base + NVE4_SU_INFO_ADDR)); - if (su->tex.format) { + if (su->op != OP_SUSTP && su->tex.format) { const TexInstruction::ImgFormatDesc *format = su->tex.format; int blockwidth = format->bits[0] + format->bits[1] + format->bits[2] + format->bits[3]; - if (blockwidth >= 8) { - // make sure that the format doesn't mismatch - bld.mkCmp(OP_SET_OR, CC_NE, TYPE_U32, pred1->getDef(0), - TYPE_U32, bld.loadImm(NULL, blockwidth / 8), - loadSuInfo32(ind, base + NVE4_SU_INFO_BSIZE), - pred1->getDef(0)); - } + // make sure that the format doesn't mismatch + assert(format->components != 0); + bld.mkCmp(OP_SET_OR, CC_NE, TYPE_U32, pred1->getDef(0), + TYPE_U32, bld.loadImm(NULL, blockwidth / 8), + loadSuInfo32(ind, base + NVE4_SU_INFO_BSIZE), + pred1->getDef(0)); } su->setPredicate(CC_NOT_P, pred1->getDef(0)); |