diff options
author | Iago Toral Quiroga <[email protected]> | 2016-01-18 11:23:33 +0100 |
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committer | Samuel Iglesias Gonsálvez <[email protected]> | 2016-05-10 11:25:08 +0200 |
commit | e0c45182e3d865d7f187dc35e70832f1fa7c9fad (patch) | |
tree | 624919ceb2af65eff7105f6ee332b14821419baa | |
parent | 80f60a4302c8bd805882baaf60db72cf785593e3 (diff) |
i965/fs: implement d2b
v2: Use subscript() instead of stride() (Curro)
Reviewed-by: Kenneth Graunke <[email protected]>
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index f4f435997fc..c456339f44e 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -1107,6 +1107,19 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) case nir_op_f2b: bld.CMP(result, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ); break; + case nir_op_d2b: { + /* two-argument instructions can't take 64-bit immediates */ + fs_reg zero = vgrf(glsl_type::double_type); + bld.MOV(zero, brw_imm_df(0.0)); + /* A SIMD16 execution needs to be split in two instructions, so use + * a vgrf instead of the flag register as dst so instruction splitting + * works + */ + fs_reg tmp = vgrf(glsl_type::double_type); + bld.CMP(tmp, op[0], zero, BRW_CONDITIONAL_NZ); + bld.MOV(result, subscript(tmp, BRW_REGISTER_TYPE_UD, 0)); + break; + } case nir_op_i2b: bld.CMP(result, op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ); break; |