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authorAnuj Phogat <[email protected]>2017-09-11 13:03:31 -0700
committerAnuj Phogat <[email protected]>2017-11-03 14:30:34 -0700
commitd3d0fe4572f62474b86ef3a68405046c68b54062 (patch)
treec0d5fb5b15db2865fe52ede250a6f5c1eb1ecf08
parent3cf4fe22199a39bde3d290e343612349866a93f9 (diff)
i965/gen10: Implement WaForceRCPFEHangWorkaround
This workaround doesn't fix any of the piglit hangs we've seen on CNL. But it might be fixing something we haven't tested yet. V2: Add the check for Post Sync Operation. Update the workaround comment. Use braces around if-else. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
-rw-r--r--src/mesa/drivers/dri/i965/brw_pipe_control.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 460b8f73b6d..f5a991539e2 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -89,6 +89,26 @@ gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw, uint32_t flags)
return 0;
}
+/* #1130 from gen10 workarounds page in h/w specs:
+ * "Enable Depth Stall on every Post Sync Op if Render target Cache Flush is
+ * not enabled in same PIPE CONTROL and Enable Pixel score board stall if
+ * Render target cache flush is enabled."
+ *
+ * Applicable to CNL B0 and C0 steppings only.
+ */
+static void
+gen10_add_rcpfe_workaround_bits(uint32_t *flags)
+{
+ if (*flags & PIPE_CONTROL_RENDER_TARGET_FLUSH) {
+ *flags = *flags | PIPE_CONTROL_STALL_AT_SCOREBOARD;
+ } else if (*flags &
+ (PIPE_CONTROL_WRITE_IMMEDIATE ||
+ PIPE_CONTROL_WRITE_DEPTH_COUNT ||
+ PIPE_CONTROL_WRITE_TIMESTAMP)) {
+ *flags = *flags | PIPE_CONTROL_DEPTH_STALL;
+ }
+}
+
static void
brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
struct brw_bo *bo, uint32_t offset, uint64_t imm)
@@ -109,6 +129,9 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
brw_emit_pipe_control_flush(brw, 0);
}
+ if (devinfo->gen == 10)
+ gen10_add_rcpfe_workaround_bits(&flags);
+
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
OUT_BATCH(flags);