diff options
| author | Kenneth Graunke <[email protected]> | 2014-04-24 13:40:53 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-11-03 15:32:49 -0800 |
| commit | d18949ad823953b446bf1cef457d4c420dc2e818 (patch) | |
| tree | 1b8884c576b536ff0bc10f561c436725190391f7 | |
| parent | 263b584d5e4bc492dcd97e0f4d6aa0d8f7af634d (diff) | |
i965/skl: Refactor surface state allocation.
We will need to allocate more DWords on Skylake.
v2: Don't mark brw_context parameter const. It's modified.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Kristian Høgsberg <[email protected]>
Reviewed-by: Anuj Phogat <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_surface_state.c | 26 |
1 files changed, 16 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index 6dd343f57f4..269d9aa1aad 100644 --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c @@ -81,6 +81,16 @@ horizontal_alignment(struct intel_mipmap_tree *mt) } } +static uint32_t * +allocate_surface_state(struct brw_context *brw, uint32_t *out_offset) +{ + int dwords = 13; + uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, + dwords * 4, 64, out_offset); + memset(surf, 0, dwords * 4); + return surf; +} + static void gen8_emit_buffer_surface_state(struct brw_context *brw, uint32_t *out_offset, @@ -92,9 +102,7 @@ gen8_emit_buffer_surface_state(struct brw_context *brw, unsigned mocs, bool rw) { - uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, - 13 * 4, 64, out_offset); - memset(surf, 0, 13 * 4); + uint32_t *surf = allocate_surface_state(brw, out_offset); surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT | surface_format << BRW_SURFACE_FORMAT_SHIFT | @@ -169,8 +177,7 @@ gen8_update_texture_surface(struct gl_context *ctx, uint32_t tex_format = translate_tex_format(brw, format, sampler->sRGBDecode); - uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, - 13 * 4, 64, surf_offset); + uint32_t *surf = allocate_surface_state(brw, surf_offset); surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT | tex_format << BRW_SURFACE_FORMAT_SHIFT | @@ -283,9 +290,8 @@ gen8_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit) uint32_t surf_index = brw->wm.prog_data->binding_table.render_target_start + unit; - uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 13 * 4, 64, - &brw->wm.base.surf_offset[surf_index]); - memset(surf, 0, 13 * 4); + uint32_t *surf = + allocate_surface_state(brw, &brw->wm.base.surf_offset[surf_index]); surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT | BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT | @@ -367,8 +373,8 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, aux_mode = GEN8_SURFACE_AUX_MODE_MCS; } - uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 13 * 4, 64, - &brw->wm.base.surf_offset[surf_index]); + uint32_t *surf = + allocate_surface_state(brw, &brw->wm.base.surf_offset[surf_index]); surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) | (is_array ? GEN7_SURFACE_IS_ARRAY : 0) | |