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authorEdward O'Callaghan <[email protected]>2016-10-11 11:43:09 +1100
committerEdward O'Callaghan <[email protected]>2016-10-12 20:12:43 +1100
commitcfbf956dfd0ea093135cd4864bf3b5b7508a54b6 (patch)
tree86894dade3eca221bf987ce8f81325fb72267097
parentfd27d5fd92b0ea42854edc59768e2e04709e179a (diff)
radv: trivial case stmt style fixups
Relocate a 'default:' to the end of a case stmt and fix an indent issue. Signed-off-by: Edward O'Callaghan <[email protected]> Reviewed-by: Thomas Helland <[email protected]>
-rw-r--r--src/amd/vulkan/radv_image.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 2223c89cf12..0dc364cc396 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -758,8 +758,6 @@ radv_image_view_init(struct radv_image_view *iview,
const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
bool is_stencil = false;
switch (image->type) {
- default:
- unreachable("bad VkImageType");
case VK_IMAGE_TYPE_1D:
case VK_IMAGE_TYPE_2D:
assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->array_size);
@@ -768,6 +766,8 @@ radv_image_view_init(struct radv_image_view *iview,
assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
<= radv_minify(image->extent.depth, range->baseMipLevel));
break;
+ default:
+ unreachable("bad VkImageType");
}
iview->image = image;
iview->bo = image->bo;
@@ -842,7 +842,7 @@ void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
case 16:
image->surface.tiling_index[0] = 11;
break;
- default: /* 32, 64 */
+ default: /* 32, 64 */
image->surface.tiling_index[0] = 12;
break;
}