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authorKristian Høgsberg Kristensen <[email protected]>2016-01-21 14:14:01 -0800
committerKristian Høgsberg Kristensen <[email protected]>2016-01-21 14:18:52 -0800
commitac60e98a582737897b6e1f858023eba0543d10f3 (patch)
tree94cc415dacf77d480bf372d3e148c58890d53f2c
parent9eab8fc6834bc3b71b0ac477d09252bfac22c605 (diff)
vk: Do render cache flush for GEN8+
This is needed for SKL as well.
-rw-r--r--src/vulkan/genX_cmd_buffer.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vulkan/genX_cmd_buffer.c b/src/vulkan/genX_cmd_buffer.c
index 4f7054f83d2..1ab17470932 100644
--- a/src/vulkan/genX_cmd_buffer.c
+++ b/src/vulkan/genX_cmd_buffer.c
@@ -48,7 +48,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
scratch_bo = &device->scratch_block_pool.bo;
/* XXX: Do we need this on more than just BDW? */
-#if (ANV_GEN == 8)
+#if (ANV_GEN >= 8)
/* Emit a render target cache flush.
*
* This isn't documented anywhere in the PRM. However, it seems to be
@@ -56,7 +56,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
* this, we get GPU hangs when using multi-level command buffers which
* clear depth, reset state base address, and then go render stuff.
*/
- anv_batch_emit(&cmd_buffer->batch, GEN8_PIPE_CONTROL,
+ anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
.RenderTargetCacheFlushEnable = true);
#endif