diff options
| author | Eric Anholt <[email protected]> | 2017-11-20 10:14:38 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2017-11-20 13:54:45 -0800 |
| commit | 494effd242d9311f5ff1c923d55322970e4296bc (patch) | |
| tree | 7a48a284dffe13513e9b9946c2ec530cd000b4a8 | |
| parent | 9d5972da801e15670f95bc57e87ac823a797ee05 (diff) | |
broadcom/vc5: Align 1D texture miplevels to 64b.
Fixes tex-miplevel-selection GL2:texture() 1D
| -rw-r--r-- | src/gallium/drivers/vc5/vc5_resource.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/drivers/vc5/vc5_resource.c b/src/gallium/drivers/vc5/vc5_resource.c index dad238f89fb..768f8d41f08 100644 --- a/src/gallium/drivers/vc5/vc5_resource.c +++ b/src/gallium/drivers/vc5/vc5_resource.c @@ -442,6 +442,8 @@ vc5_setup_slices(struct vc5_resource *rsc) if (!rsc->tiled) { slice->tiling = VC5_TILING_RASTER; + if (prsc->target == PIPE_TEXTURE_1D) + level_width = align(level_width, 64 / rsc->cpp); } else { if ((i != 0 || !uif_top) && (level_width <= utile_w || |