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authorCarlos Xiong <[email protected]>2014-12-14 22:50:15 -0500
committerMarek Olšák <[email protected]>2017-03-30 14:44:33 +0200
commit3bd1380ab2aea14d6187110982b8ba576eefb073 (patch)
tree5d0794d76459174ad6cde9416558a1405f520743
parent8b110f03191624b4a41c729297ecc58adeca2e31 (diff)
amdgpu/addrlib: force all zero tile info for linear general.
-rw-r--r--src/amd/addrlib/r800/ciaddrlib.cpp11
1 files changed, 10 insertions, 1 deletions
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index f72f5a26935..d4f8c641b37 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -555,7 +555,16 @@ ADDR_E_RETURNCODE CiAddrLib::HwlSetupTileCfg(
// Global flag to control usage of tileIndex
if (UseTileIndex(index))
{
- if (static_cast<UINT_32>(index) >= m_noOfEntries)
+ if (index == TileIndexLinearGeneral)
+ {
+ pInfo->banks = 2;
+ pInfo->bankWidth = 1;
+ pInfo->bankHeight = 1;
+ pInfo->macroAspectRatio = 1;
+ pInfo->tileSplitBytes = 64;
+ pInfo->pipeConfig = ADDR_PIPECFG_P2;
+ }
+ else if (static_cast<UINT_32>(index) >= m_noOfEntries)
{
returnCode = ADDR_INVALIDPARAMS;
}