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authorMarek Olšák <[email protected]>2016-04-17 15:18:31 +0200
committerMarek Olšák <[email protected]>2016-04-18 19:51:24 +0200
commit28c2573b4f1b311145b3f21a1794adb3dcd5f61a (patch)
treebba5b73768051ad9ab8e4277a078fc0eba15038e
parent97c328b2a39ec3a7ae617d913efa7e6bf1df4d07 (diff)
radeonsi: don't flush CB/DB caches for performance counters
I'm not sure about this. This will make the engines go idle, but the caches will be unflushed. This should match app behavior without performance counters, which can be a good thing. Reviewed-by: Nicolai Hähnle <[email protected]>
-rw-r--r--src/gallium/drivers/radeonsi/si_perfcounter.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c
index 24855e4e6f2..04da197e70a 100644
--- a/src/gallium/drivers/radeonsi/si_perfcounter.c
+++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
@@ -591,9 +591,12 @@ static void si_pc_emit_stop(struct r600_common_context *ctx,
struct radeon_winsys_cs *cs = ctx->gfx.cs;
if (ctx->screen->chip_class == CIK) {
- /* Workaround for cache flush problems: send two EOP events. */
+ /* Two EOP events are required to make all engines go idle
+ * (and optional cache flushes executed) before the timestamp
+ * is written.
+ */
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
- radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) |
+ radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
EVENT_INDEX(5));
radeon_emit(cs, va);
radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
@@ -602,7 +605,7 @@ static void si_pc_emit_stop(struct r600_common_context *ctx,
}
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
- radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) |
+ radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
EVENT_INDEX(5));
radeon_emit(cs, va);
radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));