diff options
| author | Timothy Arceri <[email protected]> | 2016-10-19 12:28:14 +1100 |
|---|---|---|
| committer | Timothy Arceri <[email protected]> | 2016-10-26 14:29:36 +1100 |
| commit | 0ab51f8e164b33c5e3bc6836d0574080ef9d1dd8 (patch) | |
| tree | 921852e9d198948f208a29b9d9f59b1820b946b6 | |
| parent | 92f77e9c01085c6babe6ce80dfe4e0e7abab61a1 (diff) | |
i965: switch vs over to shared shader_info
Note we access shader_info from the program struct rather than the
nir_shader pointer because shader cache won't create a nir_shader.
Reviewed-by: Jason Ekstrand <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_draw.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vs.c | 5 |
2 files changed, 3 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index a2e044275af..92a500cfc00 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -302,7 +302,7 @@ brw_merge_inputs(struct brw_context *brw, } if (brw->gen < 8 && !brw->is_haswell) { - uint64_t mask = ctx->VertexProgram._Current->Base.nir->info->inputs_read; + uint64_t mask = ctx->VertexProgram._Current->Base.info.inputs_read; /* Prior to Haswell, the hardware can't natively support GL_FIXED or * 2_10_10_10_REV vertex formats. Set appropriate workaround flags. */ diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c index f24a2eeb553..a7f89f390dd 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.c +++ b/src/mesa/drivers/dri/i965/brw_vs.c @@ -150,9 +150,8 @@ brw_codegen_vs_prog(struct brw_context *brw, } uint64_t outputs_written = - brw_vs_outputs_written(brw, key, - vp->program.Base.nir->info->outputs_written); - prog_data.inputs_read = vp->program.Base.nir->info->inputs_read; + brw_vs_outputs_written(brw, key, vp->program.Base.info.outputs_written); + prog_data.inputs_read = vp->program.Base.info.inputs_read; if (key->copy_edgeflag) { prog_data.inputs_read |= VERT_BIT_EDGEFLAG; |