i965: set the source width/stride when handling reladdr dests in the VS.

This is a requirement specified in the docs.  No behavior change in
glsl-vs-varying-array.shader_test that violated these requirements.

1 files changed, 6 insertions, 0 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 1d88c6b5a46..49ef9742a25 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1069,6 +1069,12 @@ move_to_reladdr_dst(struct brw_vs_compile *c,
    struct brw_reg indirect = brw_vec4_indirect(0,0);
    struct brw_reg acc = retype(vec1(get_tmp(c)), BRW_REGISTER_TYPE_UW);
 
+   /* Because destination register indirect addressing can only use
+    * one index, we'll write each vertex's vec4 value separately.
+    */
+   val.width = BRW_WIDTH_4;
+   val.vstride = BRW_VERTICAL_STRIDE_4;
+
    brw_push_insn_state(p);
    brw_set_access_mode(p, BRW_ALIGN_1);