diff options
author | Christoph Bumiller <[email protected]> | 2012-03-22 11:58:31 +0100 |
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committer | Christoph Bumiller <[email protected]> | 2012-04-14 21:54:02 +0200 |
commit | be161e66d6108e56d40c116a4ee12668d6b8d960 (patch) | |
tree | d41708b22b29e0b58c290fd1449857777bebc198 | |
parent | 44e84d6f161e95d44d847440b3bc6d670c242cd7 (diff) |
nv50/ir/opt: check BB equality before instruction ordering in CSE
-rw-r--r-- | src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp index 35ddca34b19..259bb5636c5 100644 --- a/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp +++ b/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp @@ -2096,7 +2096,7 @@ LocalCSE::visit(BasicBlock *bb) for (Value::UseIterator it = src->uses.begin(); it != src->uses.end(); ++it) { Instruction *ik = (*it)->getInsn(); - if (ik && ik->serial < ir->serial && ik->bb == ir->bb) + if (ik && ik->bb == ir->bb && ik->serial < ir->serial) if (tryReplace(&ir, ik)) break; } |