diff options
| author | Chad Versace <[email protected]> | 2013-07-18 09:58:06 -0700 |
|---|---|---|
| committer | Chad Versace <[email protected]> | 2013-07-18 16:18:21 -0700 |
| commit | a16d47465ecdbaef0548207c1bc037493a67ebec (patch) | |
| tree | d6b260f55bfe7ebf9b596f45ec8999d42de89de5 | |
| parent | eb83079b35ec0a72e4c913c2c6a6f5a92a12bb9f (diff) | |
i965/hsw: Change L3 MOCS of 3DSTATE_VERTEX_BUFFERS
Change from "not cacheable" to "cacheable" in L3.
Do so for the draw upload path and blorp.
Reviewed-by: Kenneth Graunke <[email protected]>
Signed-off-by: Chad Versace <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_draw_upload.c | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_blorp.cpp | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 2952027ebd7..897e7331338 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -658,6 +658,9 @@ static void brw_emit_vertices(struct brw_context *brw) if (brw->gen >= 7) dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE; + if (brw->is_haswell) + dw0 |= GEN7_MOCS_L3 << 16; + OUT_BATCH(dw0 | (buffer->stride << BRW_VB0_PITCH_SHIFT)); OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->offset); if (brw->gen >= 5) { diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 8056bf557a1..a4a90817a8c 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -163,6 +163,9 @@ gen6_blorp_emit_vertices(struct brw_context *brw, if (brw->gen >= 7) dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE; + if (brw->is_haswell) + dw0 |= GEN7_MOCS_L3 << 16; + BEGIN_BATCH(batch_length); OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2)); OUT_BATCH(dw0); |