diff options
| author | Matt Turner <[email protected]> | 2014-08-18 23:14:44 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2014-12-05 16:43:31 -0800 |
| commit | 92346db0578ef4796ced402ff33117713da7b9ee (patch) | |
| tree | 91bb7bd04bc38d76f1223770e0ec92af6926ad68 | |
| parent | 9ed8d00ab546c8d3eadbefa5a6c553cbf9ebebeb (diff) | |
i965: Set the region of LINE's src0 to <0,1,0>.
The PRMs say that
<src0> region must be a replicated scalar
(with HorzStride = VertStride = 0).
but apparently that doesn't actually apply to all generations. I did
notice when implementing the optimization later in this series that G45
and ILK needed this regioning.
Reviewed-by: Ian Romanick <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index c4753933b40..782706a82af 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -1040,7 +1040,6 @@ ALU2(DP4) ALU2(DPH) ALU2(DP3) ALU2(DP2) -ALU2(LINE) ALU2(PLN) ALU3F(MAD) ALU3F(LRP) @@ -1136,6 +1135,16 @@ brw_MUL(struct brw_compile *p, struct brw_reg dest, } brw_inst * +brw_LINE(struct brw_compile *p, struct brw_reg dest, + struct brw_reg src0, struct brw_reg src1) +{ + src0.vstride = BRW_VERTICAL_STRIDE_0; + src0.width = BRW_WIDTH_1; + src0.hstride = BRW_HORIZONTAL_STRIDE_0; + return brw_alu2(p, BRW_OPCODE_LINE, dest, src0, src1); +} + +brw_inst * brw_F32TO16(struct brw_compile *p, struct brw_reg dst, struct brw_reg src) { const struct brw_context *brw = p->brw; |