diff options
| author | Eric Anholt <[email protected]> | 2011-05-12 08:49:53 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2011-05-18 13:57:17 -0700 |
| commit | 4bbc7915f16a8b0dcead3f34aa1b4f0328147bea (patch) | |
| tree | d296a51de641f2558b7faac20d3b6e5e9c9c84e3 | |
| parent | b126a0c0cb30b1e2f2df1953fe14d8596d1cf4f7 (diff) | |
i965/fs: Fix GPU hang on texture2d-bias on pre-Ironlake.
In the 16-wide rework, I missed that we were setting some things to be
SIMD16 mode (corresponding to their setup in emit_texture_gen4()).
Reviewed-by: Kenneth Graunke <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.cpp | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 1943ab6021f..75454be13ed 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -2531,11 +2531,8 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) int rlen = 4; uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8; - if (c->dispatch_width == 16) { - rlen = 8; - dst = vec16(dst); + if (c->dispatch_width == 16) simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; - } if (intel->gen >= 5) { switch (inst->opcode) { @@ -2570,6 +2567,7 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) /* Note that G45 and older determines shadow compare and dispatch width * from message length for most messages. */ + assert(c->dispatch_width == 8); msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE; if (inst->shadow_compare) { assert(inst->mlen == 6); @@ -2604,6 +2602,11 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) } assert(msg_type != -1); + if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) { + rlen = 8; + dst = vec16(dst); + } + brw_SAMPLE(p, retype(dst, BRW_REGISTER_TYPE_UW), inst->base_mrf, |