diff options
| author | Marek Olšák <[email protected]> | 2011-10-25 01:44:45 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2011-12-13 18:41:17 +0100 |
| commit | 41b75dc92c921c078e64962f47b3d51b1e4f7b5a (patch) | |
| tree | 6954732b29633beeaa9c2e8d95adcf49c5383908 | |
| parent | df809ae92343bb83c162ea4c807cefb67686717d (diff) | |
winsys/radeon: add flush option not to rewrite tiling flags in registers
Not used yet.
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 19 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_cs.h | 5 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_winsys.h | 4 |
3 files changed, 24 insertions, 4 deletions
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c index 8d5a6b33a7e..2239059cc53 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c @@ -71,6 +71,13 @@ #include <stdint.h> #include <xf86drm.h> +#ifndef RADEON_CHUNK_ID_FLAGS +#define RADEON_CHUNK_ID_FLAGS 0x03 + +/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ +#define RADEON_CS_KEEP_TILING_FLAGS 0x01 +#endif + #define RELOC_DWORDS (sizeof(struct drm_radeon_cs_reloc) / sizeof(uint32_t)) static boolean radeon_init_cs_context(struct radeon_cs_context *csc, int fd) @@ -96,11 +103,14 @@ static boolean radeon_init_cs_context(struct radeon_cs_context *csc, int fd) csc->chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS; csc->chunks[1].length_dw = 0; csc->chunks[1].chunk_data = (uint64_t)(uintptr_t)csc->relocs; + csc->chunks[2].chunk_id = RADEON_CHUNK_ID_FLAGS; + csc->chunks[2].length_dw = 1; + csc->chunks[2].chunk_data = (uint64_t)(uintptr_t)&csc->flags; csc->chunk_array[0] = (uint64_t)(uintptr_t)&csc->chunks[0]; csc->chunk_array[1] = (uint64_t)(uintptr_t)&csc->chunks[1]; + csc->chunk_array[2] = (uint64_t)(uintptr_t)&csc->chunks[2]; - csc->cs.num_chunks = 2; csc->cs.chunks = (uint64_t)(uintptr_t)csc->chunk_array; return TRUE; } @@ -427,6 +437,13 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs, unsigned flags) p_atomic_inc(&cs->cst->relocs_bo[i]->num_active_ioctls); } + if (flags & RADEON_FLUSH_KEEP_TILING_FLAGS) { + cs->cst->cs.num_chunks = 3; + cs->cst->flags = RADEON_CS_KEEP_TILING_FLAGS; + } else { + cs->cst->cs.num_chunks = 2; + } + if (cs->thread && (flags & RADEON_FLUSH_ASYNC)) { cs->flush_started = 1; diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h index f316b5ecd55..904000d6933 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h @@ -35,8 +35,9 @@ struct radeon_cs_context { int fd; struct drm_radeon_cs cs; - struct drm_radeon_cs_chunk chunks[2]; - uint64_t chunk_array[2]; + struct drm_radeon_cs_chunk chunks[3]; + uint64_t chunk_array[3]; + uint32_t flags; /* Relocs. */ unsigned nrelocs; diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h index c4ea6557e10..ea335d87113 100644 --- a/src/gallium/winsys/radeon/drm/radeon_winsys.h +++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h @@ -45,7 +45,9 @@ #include "pipe/p_state.h" #define RADEON_MAX_CMDBUF_DWORDS (16 * 1024) -#define RADEON_FLUSH_ASYNC (1 << 0) + +#define RADEON_FLUSH_ASYNC (1 << 0) +#define RADEON_FLUSH_KEEP_TILING_FLAGS (1 << 1) /* needs DRM 2.12.0 */ /* Tiling flags. */ enum radeon_bo_layout { |