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authorTopi Pohjolainen <[email protected]>2014-04-19 02:02:42 +0300
committerTopi Pohjolainen <[email protected]>2014-05-15 21:39:33 +0300
commit9d752c098c5dc819fd08b9611ca52d847c1b9495 (patch)
tree5568e203fd571e806c08c2d3f815663b4e405b03
parent36caae48b25b29310be1b7cbbafe7461bb51248d (diff)
i965: Extend brw_get_rb_for_first_slice() for specified level/layer
v2: Configure stencil directly for final dimensions instead of adjusting bit by bit for tiling, mip level and msaa. v3 (Ken): Used non-static constant for horizontal alignment Cc: "10.2" <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h4
-rw-r--r--src/mesa/drivers/dri/i965/brw_meta_updownsample.c32
2 files changed, 29 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 92e1592bfa4..6d4a5b58b41 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1475,6 +1475,10 @@ GLboolean brwCreateContext(gl_api api,
/*======================================================================
* brw_misc_state.c
*/
+GLuint brw_get_rb_for_slice(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ unsigned level, unsigned layer, bool flat);
+
void brw_meta_updownsample(struct brw_context *brw,
struct intel_mipmap_tree *src,
struct intel_mipmap_tree *dst);
diff --git a/src/mesa/drivers/dri/i965/brw_meta_updownsample.c b/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
index a35b7e14f61..21507b1ad2a 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
@@ -45,8 +45,10 @@
*
* Clobbers the current renderbuffer binding (ctx->CurrentRenderbuffer).
*/
-static GLuint
-brw_get_rb_for_first_slice(struct brw_context *brw, struct intel_mipmap_tree *mt)
+GLuint
+brw_get_rb_for_slice(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ unsigned level, unsigned layer, bool flat)
{
struct gl_context *ctx = &brw->ctx;
GLuint rbo;
@@ -65,9 +67,25 @@ brw_get_rb_for_first_slice(struct brw_context *brw, struct intel_mipmap_tree *mt
rb->Format = mt->format;
rb->_BaseFormat = _mesa_get_format_base_format(mt->format);
- rb->NumSamples = mt->num_samples;
- rb->Width = mt->logical_width0;
- rb->Height = mt->logical_height0;
+ /* Program takes care of msaa and mip-level access manually for stencil.
+ * The surface is also treated as Y-tiled instead of as W-tiled calling for
+ * twice the width and half the height in dimensions.
+ */
+ if (flat) {
+ const unsigned halign_stencil = 8;
+
+ rb->NumSamples = 0;
+ rb->Width = ALIGN(mt->total_width, halign_stencil) * 2;
+ rb->Height = (mt->total_height / mt->physical_depth0) / 2;
+ irb->mt_level = 0;
+ } else {
+ rb->NumSamples = mt->num_samples;
+ rb->Width = mt->logical_width0;
+ rb->Height = mt->logical_height0;
+ irb->mt_level = level;
+ }
+
+ irb->mt_layer = layer;
intel_miptree_reference(&irb->mt, mt);
@@ -102,8 +120,8 @@ brw_meta_updownsample(struct brw_context *brw,
_mesa_meta_begin(ctx, MESA_META_ALL);
_mesa_GenFramebuffers(2, fbos);
- src_rbo = brw_get_rb_for_first_slice(brw, src_mt);
- dst_rbo = brw_get_rb_for_first_slice(brw, dst_mt);
+ src_rbo = brw_get_rb_for_slice(brw, src_mt, 0, 0, false);
+ dst_rbo = brw_get_rb_for_slice(brw, dst_mt, 0, 0, false);
src_fbo = fbos[0];
dst_fbo = fbos[1];