radeon: cleanup radeon shared code after r300 and r600 classic drivers removal

Signed-off-by: Dave Airlie <[email protected]>

10 files changed, 39 insertions, 958 deletions

diff --git a/include/pci_ids/r600_pci_ids.h b/include/pci_ids/r600_pci_ids.h
index 725270a2aa0..e9defc3f3be 100644
--- a/include/pci_ids/r600_pci_ids.h
+++ b/include/pci_ids/r600_pci_ids.h
@@ -205,7 +205,6 @@ CHIPSET(0x964a, SUMO_964A,  SUMO)
 CHIPSET(0x964e, SUMO_964E,  SUMO)
 CHIPSET(0x964f, SUMO_964F,  SUMO)
 
-#ifndef RADEON_CLASSIC
 CHIPSET(0x6700, CAYMAN_6700, CAYMAN)
 CHIPSET(0x6701, CAYMAN_6701, CAYMAN)
 CHIPSET(0x6702, CAYMAN_6702, CAYMAN)
@@ -221,7 +220,6 @@ CHIPSET(0x6719, CAYMAN_6719, CAYMAN)
 CHIPSET(0x671C, CAYMAN_671C, CAYMAN)
 CHIPSET(0x671D, CAYMAN_671D, CAYMAN)
 CHIPSET(0x671F, CAYMAN_671F, CAYMAN)
-#endif
 
 CHIPSET(0x6720, BARTS_6720, BARTS)
 CHIPSET(0x6721, BARTS_6721, BARTS)
diff --git a/src/mesa/drivers/dri/radeon/radeon_chipset.h b/src/mesa/drivers/dri/radeon/radeon_chipset.h
index fd64e2180cb..445e0854fc4 100644
--- a/src/mesa/drivers/dri/radeon/radeon_chipset.h
+++ b/src/mesa/drivers/dri/radeon/radeon_chipset.h
@@ -6,77 +6,38 @@
 /* General chip classes:
  * r100 includes R100, RV100, RV200, RS100, RS200, RS250.
  * r200 includes R200, RV250, RV280, RS300.
- * r300 includes R300, RV350, RV370.
  * (RS* denotes IGP)
  */
 
 enum {
-#define RADEON_CLASSIC 1
 #define CHIPSET(id, name, family) PCI_CHIP_##name = id,
+#if defined(RADEON_R100)
 #include "pci_ids/radeon_pci_ids.h"
+#elif defined(RADEON_R200)
 #include "pci_ids/r200_pci_ids.h"
-#include "pci_ids/r300_pci_ids.h"
-#include "pci_ids/r600_pci_ids.h"
+#endif
 #undef CHIPSET
 };
 
 enum {
+#if defined(RADEON_R100)
    CHIP_FAMILY_R100,
    CHIP_FAMILY_RV100,
    CHIP_FAMILY_RS100,
    CHIP_FAMILY_RV200,
    CHIP_FAMILY_RS200,
+#elif defined(RADEON_R200)
    CHIP_FAMILY_R200,
    CHIP_FAMILY_RV250,
    CHIP_FAMILY_RS300,
    CHIP_FAMILY_RV280,
-   CHIP_FAMILY_R300,
-   CHIP_FAMILY_R350,
-   CHIP_FAMILY_RV350,
-   CHIP_FAMILY_RV380,
-   CHIP_FAMILY_RS400,
-   CHIP_FAMILY_R420,
-   CHIP_FAMILY_RV410,
-   CHIP_FAMILY_RS600,
-   CHIP_FAMILY_RS690,
-   CHIP_FAMILY_RS740,
-   CHIP_FAMILY_RV515,
-   CHIP_FAMILY_R520,
-   CHIP_FAMILY_RV530,
-   CHIP_FAMILY_R580,
-   CHIP_FAMILY_RV560,
-   CHIP_FAMILY_RV570,
-   CHIP_FAMILY_R600,
-   CHIP_FAMILY_RV610,
-   CHIP_FAMILY_RV630,
-   CHIP_FAMILY_RV670,
-   CHIP_FAMILY_RV620,
-   CHIP_FAMILY_RV635,
-   CHIP_FAMILY_RS780,
-   CHIP_FAMILY_RS880,
-   CHIP_FAMILY_RV770,
-   CHIP_FAMILY_RV730,
-   CHIP_FAMILY_RV710,
-   CHIP_FAMILY_RV740,
-   CHIP_FAMILY_CEDAR,
-   CHIP_FAMILY_REDWOOD,
-   CHIP_FAMILY_JUNIPER,
-   CHIP_FAMILY_CYPRESS,
-   CHIP_FAMILY_HEMLOCK,
-   CHIP_FAMILY_PALM,
-   CHIP_FAMILY_SUMO,
-   CHIP_FAMILY_SUMO2,
-   CHIP_FAMILY_BARTS,
-   CHIP_FAMILY_TURKS,
-   CHIP_FAMILY_CAICOS,
+#endif
    CHIP_FAMILY_LAST
 };
 
 /* General classes of Radeons, as described above the device ID section */
 #define RADEON_CLASS_R100		(0 << 0)
 #define RADEON_CLASS_R200		(1 << 0)
-#define RADEON_CLASS_R300		(2 << 0)
-#define RADEON_CLASS_R600		(3 << 0)
 #define RADEON_CLASS_MASK		(3 << 0)
 
 #define RADEON_CHIPSET_TCL		(1 << 2)	/* tcl support - any radeon */
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 87f4776ccf5..bb0168e6cd9 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -53,54 +53,18 @@ int RADEON_DEBUG = (0);
 static const char* get_chip_family_name(int chip_family)
 {
 	switch(chip_family) {
+#if defined(RADEON_R100)
 	case CHIP_FAMILY_R100: return "R100";
 	case CHIP_FAMILY_RV100: return "RV100";
 	case CHIP_FAMILY_RS100: return "RS100";
 	case CHIP_FAMILY_RV200: return "RV200";
 	case CHIP_FAMILY_RS200: return "RS200";
+#elif defined(RADEON_R200)
 	case CHIP_FAMILY_R200: return "R200";
 	case CHIP_FAMILY_RV250: return "RV250";
 	case CHIP_FAMILY_RS300: return "RS300";
 	case CHIP_FAMILY_RV280: return "RV280";
-	case CHIP_FAMILY_R300: return "R300";
-	case CHIP_FAMILY_R350: return "R350";
-	case CHIP_FAMILY_RV350: return "RV350";
-	case CHIP_FAMILY_RV380: return "RV380";
-	case CHIP_FAMILY_R420: return "R420";
-	case CHIP_FAMILY_RV410: return "RV410";
-	case CHIP_FAMILY_RS400: return "RS400";
-	case CHIP_FAMILY_RS600: return "RS600";
-	case CHIP_FAMILY_RS690: return "RS690";
-	case CHIP_FAMILY_RS740: return "RS740";
-	case CHIP_FAMILY_RV515: return "RV515";
-	case CHIP_FAMILY_R520: return "R520";
-	case CHIP_FAMILY_RV530: return "RV530";
-	case CHIP_FAMILY_R580: return "R580";
-	case CHIP_FAMILY_RV560: return "RV560";
-	case CHIP_FAMILY_RV570: return "RV570";
-	case CHIP_FAMILY_R600: return "R600";
-	case CHIP_FAMILY_RV610: return "RV610";
-	case CHIP_FAMILY_RV630: return "RV630";
-	case CHIP_FAMILY_RV670: return "RV670";
-	case CHIP_FAMILY_RV620: return "RV620";
-	case CHIP_FAMILY_RV635: return "RV635";
-	case CHIP_FAMILY_RS780: return "RS780";
-	case CHIP_FAMILY_RS880: return "RS880";
-	case CHIP_FAMILY_RV770: return "RV770";
-	case CHIP_FAMILY_RV730: return "RV730";
-	case CHIP_FAMILY_RV710: return "RV710";
-	case CHIP_FAMILY_RV740: return "RV740";
-	case CHIP_FAMILY_CEDAR: return "CEDAR";
-	case CHIP_FAMILY_REDWOOD: return "REDWOOD";
-	case CHIP_FAMILY_JUNIPER: return "JUNIPER";
-	case CHIP_FAMILY_CYPRESS: return "CYPRESS";
-	case CHIP_FAMILY_HEMLOCK: return "HEMLOCK";
-	case CHIP_FAMILY_PALM: return "PALM";
-	case CHIP_FAMILY_SUMO: return "SUMO";
-	case CHIP_FAMILY_SUMO2: return "SUMO2";
-	case CHIP_FAMILY_BARTS: return "BARTS";
-	case CHIP_FAMILY_TURKS: return "TURKS";
-	case CHIP_FAMILY_CAICOS: return "CAICOS";
+#endif
 	default: return "unknown";
 	}
 }
@@ -122,16 +86,14 @@ static const GLubyte *radeonGetString(struct gl_context * ctx, GLenum name)
 		unsigned offset;
 		GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 :
 			radeon->radeonScreen->AGPMode;
-		const char* chipclass;
 		char hardwarename[32];
 
-		if (IS_R200_CLASS(radeon->radeonScreen))
-			chipclass = "R200";
-		else
-			chipclass = "R100";
-
 		sprintf(hardwarename, "%s (%s %04X)",
-		        chipclass,
+#if defined(RADEON_R100)
+		        "R100",
+#elif defined(RADEON_R200)
+		        "R200",
+#endif
 		        get_chip_family_name(radeon->radeonScreen->chip_family),
 		        radeon->radeonScreen->device_id);
 
@@ -220,12 +182,9 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
                 radeon->texture_depth = ( glVisual->rgbBits > 16 ) ?
 	        DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
 
-	if (IS_R200_CLASS(radeon->radeonScreen) ||
-	    IS_R100_CLASS(radeon->radeonScreen)) {
-		radeon->texture_row_align = 32;
-		radeon->texture_rect_row_align = 64;
-		radeon->texture_compressed_row_align = 32;
-	}
+	radeon->texture_row_align = 32;
+	radeon->texture_rect_row_align = 64;
+	radeon->texture_compressed_row_align = 32;
 
 	radeon_init_dma(radeon);
 
@@ -251,7 +210,7 @@ static void radeon_destroy_atom_list(radeonContextPtr radeon)
 
 /**
  * Cleanup common context fields.
- * Called by r200DestroyContext/r300DestroyContext
+ * Called by r200DestroyContext
  */
 void radeonDestroyContext(__DRIcontext *driContextPriv )
 {
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index 1ae4f878a89..2e25fb13c2a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -216,8 +216,6 @@ struct radeon_tex_obj {
 	GLuint pp_border_color;
 	GLuint pp_cubic_faces;	/* cube face 1,2,3,4 log2 sizes */
 
-        GLuint pp_txfilter_1;	/*  r300 */
-
 	GLboolean border_fallback;
 };
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index a9901382f84..79753540996 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -156,7 +156,7 @@ static GLuint minify(GLuint size, GLuint levels)
 }
 
 
-static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
+static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
 {
 	GLuint curOffset, i, face, level;
 
@@ -182,39 +182,6 @@ static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_
 			__func__, rmesa, mt, mt->totalsize);
 }
 
-static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
-{
-	GLuint curOffset, i, level;
-
-	assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels);
-
-	curOffset = 0;
-	for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) {
-		GLuint face;
-
-		mt->levels[level].valid = 1;
-		mt->levels[level].width = minify(mt->width0, i);
-		mt->levels[level].height = minify(mt->height0, i);
-		mt->levels[level].depth = minify(mt->depth0, i);
-
-		for(face = 0; face < mt->faces; face++)
-			compute_tex_image_offset(rmesa, mt, face, level, &curOffset);
-		/* from r700? cube levels seems to be aligned to 8 faces,
-		 * as we have separate register for 1'st level offset add
-		 * 2 image alignment after 1'st mip level */
-		if(rmesa->radeonScreen->chip_family >= CHIP_FAMILY_RV770 &&
-		   mt->target == GL_TEXTURE_CUBE_MAP && level >= 1)
-			curOffset += 2 * mt->levels[level].size;
-	}
-
-	/* Note the required size in memory */
-	mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
-
-	radeon_print(RADEON_TEXTURE, RADEON_TRACE,
-			"%s(%p, %p) total size %d\n",
-			__func__, rmesa, mt, mt->totalsize);
-}
-
 /**
  * Create a new mipmap tree, calculate its layout and allocate memory.
  */
@@ -239,10 +206,7 @@ static radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa,
 	mt->depth0 = depth0;
 	mt->tilebits = tilebits;
 
-	if (rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R300)
-		calculate_miptree_layout_r300(rmesa, mt);
-	else
-		calculate_miptree_layout_r100(rmesa, mt);
+	calculate_miptree_layout(rmesa, mt);
 
 	mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
                             0, mt->totalsize, 1024,
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 3e5f46b483d..b4190eb7eb0 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -389,6 +389,7 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
    screen->device_id = device_id;
    screen->chip_flags = 0;
    switch ( device_id ) {
+#if defined(RADEON_R100)
    case PCI_CHIP_RN50_515E:
    case PCI_CHIP_RN50_5969:
 	return -1;
@@ -429,6 +430,7 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
       screen->chip_flags = RADEON_CHIPSET_TCL;
       break;
 
+#elif defined(RADEON_R200)
    case PCI_CHIP_R200_BB:
    case PCI_CHIP_R200_QH:
    case PCI_CHIP_R200_QL:
@@ -463,582 +465,7 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
    case PCI_CHIP_RS350_7835:
       screen->chip_family = CHIP_FAMILY_RS300;
       break;
-
-   case PCI_CHIP_R300_AD:
-   case PCI_CHIP_R300_AE:
-   case PCI_CHIP_R300_AF:
-   case PCI_CHIP_R300_AG:
-   case PCI_CHIP_R300_ND:
-   case PCI_CHIP_R300_NE:
-   case PCI_CHIP_R300_NF:
-   case PCI_CHIP_R300_NG:
-      screen->chip_family = CHIP_FAMILY_R300;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV350_AP:
-   case PCI_CHIP_RV350_AQ:
-   case PCI_CHIP_RV350_AR:
-   case PCI_CHIP_RV350_AS:
-   case PCI_CHIP_RV350_AT:
-   case PCI_CHIP_RV350_AV:
-   case PCI_CHIP_RV350_AU:
-   case PCI_CHIP_RV350_NP:
-   case PCI_CHIP_RV350_NQ:
-   case PCI_CHIP_RV350_NR:
-   case PCI_CHIP_RV350_NS:
-   case PCI_CHIP_RV350_NT:
-   case PCI_CHIP_RV350_NV:
-      screen->chip_family = CHIP_FAMILY_RV350;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_R350_AH:
-   case PCI_CHIP_R350_AI:
-   case PCI_CHIP_R350_AJ:
-   case PCI_CHIP_R350_AK:
-   case PCI_CHIP_R350_NH:
-   case PCI_CHIP_R350_NI:
-   case PCI_CHIP_R360_NJ:
-   case PCI_CHIP_R350_NK:
-      screen->chip_family = CHIP_FAMILY_R350;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV370_5460:
-   case PCI_CHIP_RV370_5462:
-   case PCI_CHIP_RV370_5464:
-   case PCI_CHIP_RV370_5B60:
-   case PCI_CHIP_RV370_5B62:
-   case PCI_CHIP_RV370_5B63:
-   case PCI_CHIP_RV370_5B64:
-   case PCI_CHIP_RV370_5B65:
-   case PCI_CHIP_RV380_3150:
-   case PCI_CHIP_RV380_3152:
-   case PCI_CHIP_RV380_3154:
-   case PCI_CHIP_RV380_3155:
-   case PCI_CHIP_RV380_3E50:
-   case PCI_CHIP_RV380_3E54:
-      screen->chip_family = CHIP_FAMILY_RV380;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_R420_JN:
-   case PCI_CHIP_R420_JH:
-   case PCI_CHIP_R420_JI:
-   case PCI_CHIP_R420_JJ:
-   case PCI_CHIP_R420_JK:
-   case PCI_CHIP_R420_JL:
-   case PCI_CHIP_R420_JM:
-   case PCI_CHIP_R420_JO:
-   case PCI_CHIP_R420_JP:
-   case PCI_CHIP_R420_JT:
-   case PCI_CHIP_R481_4B49:
-   case PCI_CHIP_R481_4B4A:
-   case PCI_CHIP_R481_4B4B:
-   case PCI_CHIP_R481_4B4C:
-   case PCI_CHIP_R423_UH:
-   case PCI_CHIP_R423_UI:
-   case PCI_CHIP_R423_UJ:
-   case PCI_CHIP_R423_UK:
-   case PCI_CHIP_R430_554C:
-   case PCI_CHIP_R430_554D:
-   case PCI_CHIP_R430_554E:
-   case PCI_CHIP_R430_554F:
-   case PCI_CHIP_R423_5550:
-   case PCI_CHIP_R423_UQ:
-   case PCI_CHIP_R423_UR:
-   case PCI_CHIP_R423_UT:
-   case PCI_CHIP_R430_5D48:
-   case PCI_CHIP_R430_5D49:
-   case PCI_CHIP_R430_5D4A:
-   case PCI_CHIP_R480_5D4C:
-   case PCI_CHIP_R480_5D4D:
-   case PCI_CHIP_R480_5D4E:
-   case PCI_CHIP_R480_5D4F:
-   case PCI_CHIP_R480_5D50:
-   case PCI_CHIP_R480_5D52:
-   case PCI_CHIP_R423_5D57:
-      screen->chip_family = CHIP_FAMILY_R420;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV410_5E4C:
-   case PCI_CHIP_RV410_5E4F:
-   case PCI_CHIP_RV410_564A:
-   case PCI_CHIP_RV410_564B:
-   case PCI_CHIP_RV410_564F:
-   case PCI_CHIP_RV410_5652:
-   case PCI_CHIP_RV410_5653:
-   case PCI_CHIP_RV410_5657:
-   case PCI_CHIP_RV410_5E48:
-   case PCI_CHIP_RV410_5E4A:
-   case PCI_CHIP_RV410_5E4B:
-   case PCI_CHIP_RV410_5E4D:
-      screen->chip_family = CHIP_FAMILY_RV410;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RS480_5954:
-   case PCI_CHIP_RS480_5955:
-   case PCI_CHIP_RS482_5974:
-   case PCI_CHIP_RS482_5975:
-   case PCI_CHIP_RS400_5A41:
-   case PCI_CHIP_RS400_5A42:
-   case PCI_CHIP_RC410_5A61:
-   case PCI_CHIP_RC410_5A62:
-      screen->chip_family = CHIP_FAMILY_RS400;
-      break;
-
-   case PCI_CHIP_RS600_793F:
-   case PCI_CHIP_RS600_7941:
-   case PCI_CHIP_RS600_7942:
-      screen->chip_family = CHIP_FAMILY_RS600;
-      break;
-
-   case PCI_CHIP_RS690_791E:
-   case PCI_CHIP_RS690_791F:
-      screen->chip_family = CHIP_FAMILY_RS690;
-      break;
-   case PCI_CHIP_RS740_796C:
-   case PCI_CHIP_RS740_796D:
-   case PCI_CHIP_RS740_796E:
-   case PCI_CHIP_RS740_796F:
-      screen->chip_family = CHIP_FAMILY_RS740;
-      break;
-
-   case PCI_CHIP_R520_7100:
-   case PCI_CHIP_R520_7101:
-   case PCI_CHIP_R520_7102:
-   case PCI_CHIP_R520_7103:
-   case PCI_CHIP_R520_7104:
-   case PCI_CHIP_R520_7105:
-   case PCI_CHIP_R520_7106:
-   case PCI_CHIP_R520_7108:
-   case PCI_CHIP_R520_7109:
-   case PCI_CHIP_R520_710A:
-   case PCI_CHIP_R520_710B:
-   case PCI_CHIP_R520_710C:
-   case PCI_CHIP_R520_710E:
-   case PCI_CHIP_R520_710F:
-      screen->chip_family = CHIP_FAMILY_R520;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV515_7140:
-   case PCI_CHIP_RV515_7141:
-   case PCI_CHIP_RV515_7142:
-   case PCI_CHIP_RV515_7143:
-   case PCI_CHIP_RV515_7144:
-   case PCI_CHIP_RV515_7145:
-   case PCI_CHIP_RV515_7146:
-   case PCI_CHIP_RV515_7147:
-   case PCI_CHIP_RV515_7149:
-   case PCI_CHIP_RV515_714A:
-   case PCI_CHIP_RV515_714B:
-   case PCI_CHIP_RV515_714C:
-   case PCI_CHIP_RV515_714D:
-   case PCI_CHIP_RV515_714E:
-   case PCI_CHIP_RV515_714F:
-   case PCI_CHIP_RV515_7151:
-   case PCI_CHIP_RV515_7152:
-   case PCI_CHIP_RV515_7153:
-   case PCI_CHIP_RV515_715E:
-   case PCI_CHIP_RV515_715F:
-   case PCI_CHIP_RV515_7180:
-   case PCI_CHIP_RV515_7181:
-   case PCI_CHIP_RV515_7183:
-   case PCI_CHIP_RV515_7186:
-   case PCI_CHIP_RV515_7187:
-   case PCI_CHIP_RV515_7188:
-   case PCI_CHIP_RV515_718A:
-   case PCI_CHIP_RV515_718B:
-   case PCI_CHIP_RV515_718C:
-   case PCI_CHIP_RV515_718D:
-   case PCI_CHIP_RV515_718F:
-   case PCI_CHIP_RV515_7193:
-   case PCI_CHIP_RV515_7196:
-   case PCI_CHIP_RV515_719B:
-   case PCI_CHIP_RV515_719F:
-   case PCI_CHIP_RV515_7200:
-   case PCI_CHIP_RV515_7210:
-   case PCI_CHIP_RV515_7211:
-      screen->chip_family = CHIP_FAMILY_RV515;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV530_71C0:
-   case PCI_CHIP_RV530_71C1:
-   case PCI_CHIP_RV530_71C2:
-   case PCI_CHIP_RV530_71C3:
-   case PCI_CHIP_RV530_71C4:
-   case PCI_CHIP_RV530_71C5:
-   case PCI_CHIP_RV530_71C6:
-   case PCI_CHIP_RV530_71C7:
-   case PCI_CHIP_RV530_71CD:
-   case PCI_CHIP_RV530_71CE:
-   case PCI_CHIP_RV530_71D2:
-   case PCI_CHIP_RV530_71D4:
-   case PCI_CHIP_RV530_71D5:
-   case PCI_CHIP_RV530_71D6:
-   case PCI_CHIP_RV530_71DA:
-   case PCI_CHIP_RV530_71DE:
-      screen->chip_family = CHIP_FAMILY_RV530;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_R580_7240:
-   case PCI_CHIP_R580_7243:
-   case PCI_CHIP_R580_7244:
-   case PCI_CHIP_R580_7245:
-   case PCI_CHIP_R580_7246:
-   case PCI_CHIP_R580_7247:
-   case PCI_CHIP_R580_7248:
-   case PCI_CHIP_R580_7249:
-   case PCI_CHIP_R580_724A:
-   case PCI_CHIP_R580_724B:
-   case PCI_CHIP_R580_724C:
-   case PCI_CHIP_R580_724D:
-   case PCI_CHIP_R580_724E:
-   case PCI_CHIP_R580_724F:
-   case PCI_CHIP_R580_7284:
-      screen->chip_family = CHIP_FAMILY_R580;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV570_7280:
-   case PCI_CHIP_RV560_7281:
-   case PCI_CHIP_RV560_7283:
-   case PCI_CHIP_RV560_7287:
-   case PCI_CHIP_RV570_7288:
-   case PCI_CHIP_RV570_7289:
-   case PCI_CHIP_RV570_728B:
-   case PCI_CHIP_RV570_728C:
-   case PCI_CHIP_RV560_7290:
-   case PCI_CHIP_RV560_7291:
-   case PCI_CHIP_RV560_7293:
-   case PCI_CHIP_RV560_7297:
-      screen->chip_family = CHIP_FAMILY_RV560;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_R600_9400:
-   case PCI_CHIP_R600_9401:
-   case PCI_CHIP_R600_9402:
-   case PCI_CHIP_R600_9403:
-   case PCI_CHIP_R600_9405:
-   case PCI_CHIP_R600_940A:
-   case PCI_CHIP_R600_940B:
-   case PCI_CHIP_R600_940F:
-      screen->chip_family = CHIP_FAMILY_R600;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV610_94C0:
-   case PCI_CHIP_RV610_94C1:
-   case PCI_CHIP_RV610_94C3:
-   case PCI_CHIP_RV610_94C4:
-   case PCI_CHIP_RV610_94C5:
-   case PCI_CHIP_RV610_94C6:
-   case PCI_CHIP_RV610_94C7:
-   case PCI_CHIP_RV610_94C8:
-   case PCI_CHIP_RV610_94C9:
-   case PCI_CHIP_RV610_94CB:
-   case PCI_CHIP_RV610_94CC:
-   case PCI_CHIP_RV610_94CD:
-      screen->chip_family = CHIP_FAMILY_RV610;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV630_9580:
-   case PCI_CHIP_RV630_9581:
-   case PCI_CHIP_RV630_9583:
-   case PCI_CHIP_RV630_9586:
-   case PCI_CHIP_RV630_9587:
-   case PCI_CHIP_RV630_9588:
-   case PCI_CHIP_RV630_9589:
-   case PCI_CHIP_RV630_958A:
-   case PCI_CHIP_RV630_958B:
-   case PCI_CHIP_RV630_958C:
-   case PCI_CHIP_RV630_958D:
-   case PCI_CHIP_RV630_958E:
-   case PCI_CHIP_RV630_958F:
-      screen->chip_family = CHIP_FAMILY_RV630;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV670_9500:
-   case PCI_CHIP_RV670_9501:
-   case PCI_CHIP_RV670_9504:
-   case PCI_CHIP_RV670_9505:
-   case PCI_CHIP_RV670_9506:
-   case PCI_CHIP_RV670_9507:
-   case PCI_CHIP_RV670_9508:
-   case PCI_CHIP_RV670_9509:
-   case PCI_CHIP_RV670_950F:
-   case PCI_CHIP_RV670_9511:
-   case PCI_CHIP_RV670_9515:
-   case PCI_CHIP_RV670_9517:
-   case PCI_CHIP_RV670_9519:
-      screen->chip_family = CHIP_FAMILY_RV670;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV620_95C0:
-   case PCI_CHIP_RV620_95C2:
-   case PCI_CHIP_RV620_95C4:
-   case PCI_CHIP_RV620_95C5:
-   case PCI_CHIP_RV620_95C6:
-   case PCI_CHIP_RV620_95C7:
-   case PCI_CHIP_RV620_95C9:
-   case PCI_CHIP_RV620_95CC:
-   case PCI_CHIP_RV620_95CD:
-   case PCI_CHIP_RV620_95CE:
-   case PCI_CHIP_RV620_95CF:
-      screen->chip_family = CHIP_FAMILY_RV620;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV635_9590:
-   case PCI_CHIP_RV635_9591:
-   case PCI_CHIP_RV635_9593:
-   case PCI_CHIP_RV635_9595:
-   case PCI_CHIP_RV635_9596:
-   case PCI_CHIP_RV635_9597:
-   case PCI_CHIP_RV635_9598:
-   case PCI_CHIP_RV635_9599:
-   case PCI_CHIP_RV635_959B:
-      screen->chip_family = CHIP_FAMILY_RV635;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RS780_9610:
-   case PCI_CHIP_RS780_9611:
-   case PCI_CHIP_RS780_9612:
-   case PCI_CHIP_RS780_9613:
-   case PCI_CHIP_RS780_9614:
-   case PCI_CHIP_RS780_9615:
-   case PCI_CHIP_RS780_9616:
-      screen->chip_family = CHIP_FAMILY_RS780;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-   case PCI_CHIP_RS880_9710:
-   case PCI_CHIP_RS880_9711:
-   case PCI_CHIP_RS880_9712:
-   case PCI_CHIP_RS880_9713:
-   case PCI_CHIP_RS880_9714:
-   case PCI_CHIP_RS880_9715:
-      screen->chip_family = CHIP_FAMILY_RS880;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV770_9440:
-   case PCI_CHIP_RV770_9441:
-   case PCI_CHIP_RV770_9442:
-   case PCI_CHIP_RV770_9443:
-   case PCI_CHIP_RV770_9444:
-   case PCI_CHIP_RV770_9446:
-   case PCI_CHIP_RV770_944A:
-   case PCI_CHIP_RV770_944B:
-   case PCI_CHIP_RV770_944C:
-   case PCI_CHIP_RV770_944E:
-   case PCI_CHIP_RV770_9450:
-   case PCI_CHIP_RV770_9452:
-   case PCI_CHIP_RV770_9456:
-   case PCI_CHIP_RV770_945A:
-   case PCI_CHIP_RV770_945B:
-   case PCI_CHIP_RV770_945E:
-   case PCI_CHIP_RV790_9460:
-   case PCI_CHIP_RV790_9462:
-   case PCI_CHIP_RV770_946A:
-   case PCI_CHIP_RV770_946B:
-   case PCI_CHIP_RV770_947A:
-   case PCI_CHIP_RV770_947B:
-      screen->chip_family = CHIP_FAMILY_RV770;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV730_9480:
-   case PCI_CHIP_RV730_9487:
-   case PCI_CHIP_RV730_9488:
-   case PCI_CHIP_RV730_9489:
-   case PCI_CHIP_RV730_948A:
-   case PCI_CHIP_RV730_948F:
-   case PCI_CHIP_RV730_9490:
-   case PCI_CHIP_RV730_9491:
-   case PCI_CHIP_RV730_9495:
-   case PCI_CHIP_RV730_9498:
-   case PCI_CHIP_RV730_949C:
-   case PCI_CHIP_RV730_949E:
-   case PCI_CHIP_RV730_949F:
-      screen->chip_family = CHIP_FAMILY_RV730;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV710_9540:
-   case PCI_CHIP_RV710_9541:
-   case PCI_CHIP_RV710_9542:
-   case PCI_CHIP_RV710_954E:
-   case PCI_CHIP_RV710_954F:
-   case PCI_CHIP_RV710_9552:
-   case PCI_CHIP_RV710_9553:
-   case PCI_CHIP_RV710_9555:
-   case PCI_CHIP_RV710_9557:
-   case PCI_CHIP_RV710_955F:
-      screen->chip_family = CHIP_FAMILY_RV710;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-   case PCI_CHIP_RV740_94A0:
-   case PCI_CHIP_RV740_94A1:
-   case PCI_CHIP_RV740_94A3:
-   case PCI_CHIP_RV740_94B1:
-   case PCI_CHIP_RV740_94B3:
-   case PCI_CHIP_RV740_94B4:
-   case PCI_CHIP_RV740_94B5:
-   case PCI_CHIP_RV740_94B9:
-      screen->chip_family = CHIP_FAMILY_RV740;
-      screen->chip_flags = RADEON_CHIPSET_TCL;
-      break;
-
-    case PCI_CHIP_CEDAR_68E0:
-    case PCI_CHIP_CEDAR_68E1:
-    case PCI_CHIP_CEDAR_68E4:
-    case PCI_CHIP_CEDAR_68E5:
-    case PCI_CHIP_CEDAR_68E8:
-    case PCI_CHIP_CEDAR_68E9:
-    case PCI_CHIP_CEDAR_68F1:
-    case PCI_CHIP_CEDAR_68F2:
-    case PCI_CHIP_CEDAR_68F8:
-    case PCI_CHIP_CEDAR_68F9:
-    case PCI_CHIP_CEDAR_68FE:
-       screen->chip_family = CHIP_FAMILY_CEDAR;
-       screen->chip_flags = RADEON_CHIPSET_TCL;
-       break;
-
-    case PCI_CHIP_REDWOOD_68C0:
-    case PCI_CHIP_REDWOOD_68C1:
-    case PCI_CHIP_REDWOOD_68C8:
-    case PCI_CHIP_REDWOOD_68C9:
-    case PCI_CHIP_REDWOOD_68D8:
-    case PCI_CHIP_REDWOOD_68D9:
-    case PCI_CHIP_REDWOOD_68DA:
-    case PCI_CHIP_REDWOOD_68DE:
-       screen->chip_family = CHIP_FAMILY_REDWOOD;
-       screen->chip_flags = RADEON_CHIPSET_TCL;
-       break;
-
-    case PCI_CHIP_JUNIPER_68A0:
-    case PCI_CHIP_JUNIPER_68A1:
-    case PCI_CHIP_JUNIPER_68A8:
-    case PCI_CHIP_JUNIPER_68A9:
-    case PCI_CHIP_JUNIPER_68B0:
-    case PCI_CHIP_JUNIPER_68B8:
-    case PCI_CHIP_JUNIPER_68B9:
-    case PCI_CHIP_JUNIPER_68BA:
-    case PCI_CHIP_JUNIPER_68BE:
-    case PCI_CHIP_JUNIPER_68BF:
-       screen->chip_family = CHIP_FAMILY_JUNIPER;
-       screen->chip_flags = RADEON_CHIPSET_TCL;
-       break;
-
-    case PCI_CHIP_CYPRESS_6880:
-    case PCI_CHIP_CYPRESS_6888:
-    case PCI_CHIP_CYPRESS_6889:
-    case PCI_CHIP_CYPRESS_688A:
-    case PCI_CHIP_CYPRESS_6898:
-    case PCI_CHIP_CYPRESS_6899:
-    case PCI_CHIP_CYPRESS_689B:
-    case PCI_CHIP_CYPRESS_689E:
-       screen->chip_family = CHIP_FAMILY_CYPRESS;
-       screen->chip_flags = RADEON_CHIPSET_TCL;
-       break;
-
-    case PCI_CHIP_HEMLOCK_689C:
-    case PCI_CHIP_HEMLOCK_689D:
-       screen->chip_family = CHIP_FAMILY_HEMLOCK;
-       screen->chip_flags = RADEON_CHIPSET_TCL;
-       break;
-
-    case PCI_CHIP_PALM_9802:
-    case PCI_CHIP_PALM_9803:
-    case PCI_CHIP_PALM_9804:
-    case PCI_CHIP_PALM_9805:
-    case PCI_CHIP_PALM_9806:
-    case PCI_CHIP_PALM_9807:
-       screen->chip_family = CHIP_FAMILY_PALM;
-       screen->chip_flags = RADEON_CHIPSET_TCL;
-       break;
-
-    case PCI_CHIP_SUMO_9640:
-    case PCI_CHIP_SUMO_9641:
-    case PCI_CHIP_SUMO_9647:
-    case PCI_CHIP_SUMO_9648:
-    case PCI_CHIP_SUMO_964A:
-    case PCI_CHIP_SUMO_964E:
-    case PCI_CHIP_SUMO_964F:
-       screen->chip_family = CHIP_FAMILY_SUMO;
-       screen->chip_flags = RADEON_CHIPSET_TCL;
-       break;
-
-    case PCI_CHIP_SUMO2_9642:
-    case PCI_CHIP_SUMO2_9643:
-    case PCI_CHIP_SUMO2_9644:
-    case PCI_CHIP_SUMO2_9645:
-       screen->chip_family = CHIP_FAMILY_SUMO2;
-       screen->chip_flags = RADEON_CHIPSET_TCL;
-       break;
-
-   case PCI_CHIP_BARTS_6720:
-   case PCI_CHIP_BARTS_6721:
-   case PCI_CHIP_BARTS_6722:
-   case PCI_CHIP_BARTS_6723:
-   case PCI_CHIP_BARTS_6724:
-   case PCI_CHIP_BARTS_6725:
-   case PCI_CHIP_BARTS_6726:
-   case PCI_CHIP_BARTS_6727:
-   case PCI_CHIP_BARTS_6728:
-   case PCI_CHIP_BARTS_6729:
-   case PCI_CHIP_BARTS_6738:
-   case PCI_CHIP_BARTS_6739:
-   case PCI_CHIP_BARTS_673E:
-       screen->chip_family = CHIP_FAMILY_BARTS;
-       screen->chip_flags = RADEON_CHIPSET_TCL;
-       break;
-
-   case PCI_CHIP_TURKS_6740:
-   case PCI_CHIP_TURKS_6741:
-   case PCI_CHIP_TURKS_6742:
-   case PCI_CHIP_TURKS_6743:
-   case PCI_CHIP_TURKS_6744:
-   case PCI_CHIP_TURKS_6745:
-   case PCI_CHIP_TURKS_6746:
-   case PCI_CHIP_TURKS_6747:
-   case PCI_CHIP_TURKS_6748:
-   case PCI_CHIP_TURKS_6749:
-   case PCI_CHIP_TURKS_6750:
-   case PCI_CHIP_TURKS_6758:
-   case PCI_CHIP_TURKS_6759:
-   case PCI_CHIP_TURKS_675F:
-       screen->chip_family = CHIP_FAMILY_TURKS;
-       screen->chip_flags = RADEON_CHIPSET_TCL;
-       break;
-
-   case PCI_CHIP_CAICOS_6760:
-   case PCI_CHIP_CAICOS_6761:
-   case PCI_CHIP_CAICOS_6762:
-   case PCI_CHIP_CAICOS_6763:
-   case PCI_CHIP_CAICOS_6764:
-   case PCI_CHIP_CAICOS_6765:
-   case PCI_CHIP_CAICOS_6766:
-   case PCI_CHIP_CAICOS_6767:
-   case PCI_CHIP_CAICOS_6768:
-   case PCI_CHIP_CAICOS_6770:
-   case PCI_CHIP_CAICOS_6778:
-   case PCI_CHIP_CAICOS_6779:
-       screen->chip_family = CHIP_FAMILY_CAICOS;
-       screen->chip_flags = RADEON_CHIPSET_TCL;
-       break;
+#endif
 
    default:
       fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
@@ -1089,10 +516,11 @@ radeonCreateScreen2(__DRIscreen *sPriv)
    if (getenv("R300_NO_TCL"))
 	   screen->chip_flags &= ~RADEON_CHIPSET_TCL;
 
-   if (screen->chip_family <= CHIP_FAMILY_RS200)
-	   screen->chip_flags |= RADEON_CLASS_R100;
-   else if (screen->chip_family <= CHIP_FAMILY_RV280)
-	   screen->chip_flags |= RADEON_CLASS_R200;
+#if defined(RADEON_R100)
+   screen->chip_flags |= RADEON_CLASS_R100;
+#elif defined(RADEON_R200)
+   screen->chip_flags |= RADEON_CLASS_R200;
+#endif
 
    i = 0;
    screen->extensions[i++] = &dri2ConfigQueryExtension.base;
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h
index f8f55ce89fa..1f0f383c683 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -117,10 +117,5 @@ struct __DRIimageRec {
    void *data;
 };
 
-#define IS_R100_CLASS(screen) \
-	((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R100)
-#define IS_R200_CLASS(screen) \
-	((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R200)
-
 extern void radeonDestroyBuffer(__DRIdrawable *driDrawPriv);
 #endif /* __RADEON_SCREEN_H__ */
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c
index 715b93269cc..c866aef0f1b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -341,8 +341,11 @@ static gl_format radeonChoose8888TexFormat(radeonContextPtr rmesa,
 	const GLubyte littleEndian = *((const GLubyte *)&ui);
 
 	/* r100 can only do this */
-	if (IS_R100_CLASS(rmesa->radeonScreen) || fbo)
-	  return _radeon_texformat_argb8888;
+#if defined(RADEON_R100)
+	return _radeon_texformat_argb8888;
+#elif defined(RADEON_R200)
+	if (fbo)
+		return _radeon_texformat_argb8888;
 
 	if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) ||
 	    (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) ||
@@ -354,16 +357,9 @@ static gl_format radeonChoose8888TexFormat(radeonContextPtr rmesa,
 		   (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) ||
 		   (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) {
 		return MESA_FORMAT_RGBA8888_REV;
-	} else if (IS_R200_CLASS(rmesa->radeonScreen)) {
-		return _radeon_texformat_argb8888;
-	} else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) ||
-					    srcType == GL_UNSIGNED_INT_8_8_8_8)) {
-		return MESA_FORMAT_ARGB8888_REV;
-	} else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) ||
-					    srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) {
-		return MESA_FORMAT_ARGB8888;
 	} else
 		return _radeon_texformat_argb8888;
+#endif
 }
 
 gl_format radeonChooseTextureFormat_mesa(struct gl_context * ctx,
@@ -467,12 +463,13 @@ gl_format radeonChooseTextureFormat(struct gl_context * ctx,
 	case GL_ALPHA12:
 	case GL_ALPHA16:
 	case GL_COMPRESSED_ALPHA:
+#if defined(RADEON_R200)
 		/* r200: can't use a8 format since interpreting hw I8 as a8 would result
 		   in wrong rgb values (same as alpha value instead of 0). */
-		if (IS_R200_CLASS(rmesa->radeonScreen))
-			return _radeon_texformat_al88;
-		else
-			return MESA_FORMAT_A8;
+		return _radeon_texformat_al88;
+#else
+		return MESA_FORMAT_A8;
+#endif
 	case 1:
 	case GL_LUMINANCE:
 	case GL_LUMINANCE4:
diff --git a/src/mesa/drivers/dri/radeon/server/radeon.h b/src/mesa/drivers/dri/radeon/server/radeon.h
deleted file mode 100644
index 3fb1e37c530..00000000000
--- a/src/mesa/drivers/dri/radeon/server/radeon.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/**
- * \file server/radeon.h
- * \brief Radeon 2D driver data structures.
- */
-
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- *                VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _RADEON_H_
-#define _RADEON_H_
-
-#include "xf86drm.h"		/* drm_handle_t, etc */
-
-#       define RADEON_AGP_1X_MODE           0x01
-#       define RADEON_AGP_2X_MODE           0x02
-#       define RADEON_AGP_4X_MODE           0x04
-#       define RADEON_AGP_FW_MODE           0x10
-#       define RADEON_AGP_MODE_MASK         0x17
-#define RADEON_CP_CSQ_CNTL                  0x0740
-#       define RADEON_CSQ_CNT_PRIMARY_MASK     (0xff << 0)
-#       define RADEON_CSQ_PRIDIS_INDDIS        (0    << 28)
-#       define RADEON_CSQ_PRIPIO_INDDIS        (1    << 28)
-#       define RADEON_CSQ_PRIBM_INDDIS         (2    << 28)
-#       define RADEON_CSQ_PRIPIO_INDBM         (3    << 28)
-#       define RADEON_CSQ_PRIBM_INDBM          (4    << 28)
-#       define RADEON_CSQ_PRIPIO_INDPIO        (15   << 28)
-
-#define RADEON_PCIGART_TABLE_SIZE       32768
-
-#define PCI_CHIP_R200_BB                0x4242
-#define PCI_CHIP_RV250_Id               0x4964
-#define PCI_CHIP_RV250_Ie               0x4965
-#define PCI_CHIP_RV250_If               0x4966
-#define PCI_CHIP_RV250_Ig               0x4967
-#define PCI_CHIP_RADEON_LW		0x4C57
-#define PCI_CHIP_RADEON_LX		0x4C58
-#define PCI_CHIP_RADEON_LY		0x4C59
-#define PCI_CHIP_RADEON_LZ		0x4C5A
-#define PCI_CHIP_RV250_Ld		0x4C64
-#define PCI_CHIP_RV250_Le		0x4C65
-#define PCI_CHIP_RV250_Lf		0x4C66
-#define PCI_CHIP_RV250_Lg		0x4C67
-#define PCI_CHIP_R300_ND		0x4E44
-#define PCI_CHIP_R300_NE		0x4E45
-#define PCI_CHIP_R300_NF		0x4E46
-#define PCI_CHIP_R300_NG		0x4E47
-#define PCI_CHIP_RADEON_QD		0x5144
-#define PCI_CHIP_RADEON_QE		0x5145
-#define PCI_CHIP_RADEON_QF		0x5146
-#define PCI_CHIP_RADEON_QG		0x5147
-#define PCI_CHIP_R200_QL		0x514C
-#define PCI_CHIP_R200_QN		0x514E
-#define PCI_CHIP_R200_QO		0x514F
-#define PCI_CHIP_RV200_QW		0x5157
-#define PCI_CHIP_RV200_QX		0x5158
-#define PCI_CHIP_RADEON_QY		0x5159
-#define PCI_CHIP_RADEON_QZ		0x515A
-#define PCI_CHIP_R200_Ql		0x516C
-#define PCI_CHIP_RV370_5460             0x5460
-#define PCI_CHIP_RV280_Y_		0x5960
-#define PCI_CHIP_RV280_Ya		0x5961
-#define PCI_CHIP_RV280_Yb		0x5962
-#define PCI_CHIP_RV280_Yc		0x5963
-
-/**
- * \brief Chip families.
- */
-typedef enum {
-    CHIP_FAMILY_UNKNOW,
-    CHIP_FAMILY_LEGACY,
-    CHIP_FAMILY_R128,
-    CHIP_FAMILY_M3,
-    CHIP_FAMILY_RADEON,
-    CHIP_FAMILY_VE,
-    CHIP_FAMILY_M6,
-    CHIP_FAMILY_RV200,
-    CHIP_FAMILY_M7,
-    CHIP_FAMILY_R200,
-    CHIP_FAMILY_RV250,
-    CHIP_FAMILY_M9,
-    CHIP_FAMILY_RV280,
-    CHIP_FAMILY_R300,
-    CHIP_FAMILY_R350,
-    CHIP_FAMILY_RV350,
-    CHIP_FAMILY_RV380,  /* RV370/RV380/M22/M24 */
-    CHIP_FAMILY_R420,   /* R420/R423/M18 */
-} RADEONChipFamily;
-
-
-typedef unsigned long memType;
-
-
-/**
- * \brief Radeon DDX driver private data.
- */
-typedef struct {
-   int               Chipset;          /**< \brief Chipset number */
-   RADEONChipFamily  ChipFamily;       /**< \brief Chip family */
-
-   unsigned long     LinearAddr;       /**< \brief Frame buffer physical address */
-
-
-   drmSize           registerSize;     /**< \brief MMIO register map size */
-   drm_handle_t         registerHandle;   /**< \brief MMIO register map handle */
-
-   int               IsPCI;            /* Current card is a PCI card */
-   
-   /**
-    * \name AGP
-    */
-   /*@{*/
-   drmSize           gartSize;          /**< \brief AGP map size */
-   drm_handle_t         gartMemHandle;     /**< \brief AGP map handle */
-   unsigned long     gartOffset;        /**< \brief AGP offset */
-   int               gartMode;          /**< \brief AGP mode */
-   int               gartFastWrite;
-   /*@}*/
-
-   /**
-    * \name CP ring buffer data
-    */
-   /*@{*/
-   unsigned long     ringStart;        /**< \brief Offset into AGP space */
-   drm_handle_t         ringHandle;       /**< \brief Handle from drmAddMap() */
-   drmSize           ringMapSize;      /**< \brief Size of map */
-   int               ringSize;         /**< \brief Size of ring (in MB) */
-
-   unsigned long     ringReadOffset;   /**< \brief Read offset into AGP space */
-   drm_handle_t         ringReadPtrHandle;/**< \brief Handle from drmAddMap() */
-   drmSize           ringReadMapSize;  /**< \brief Size of map */
-   /*@}*/
-
-   /**
-    * \name CP vertex/indirect buffer data
-    */
-   /*@{*/
-   unsigned long     bufStart;         /**< \brief Offset into AGP space */
-   drm_handle_t         bufHandle;        /**< \brief Handle from drmAddMap() */
-   drmSize           bufMapSize;       /**< \brief Size of map */
-   int               bufSize;          /**< \brief Size of buffers (in MB) */
-   int               bufNumBufs;       /**< \brief Number of buffers */
-   /*@}*/
-
-   /**
-    * \name CP AGP Texture data
-    */
-   /*@{*/
-   unsigned long     gartTexStart;      /**< \brief Offset into AGP space */
-   drm_handle_t         gartTexHandle;     /**< \brief Handle from drmAddMap() */
-   drmSize           gartTexMapSize;    /**< \brief Size of map */
-   int               gartTexSize;       /**< \brief Size of AGP tex space (in MB) */
-   int               log2GARTTexGran;
-   /*@}*/
-
-   int               drmMinor;         /**< \brief DRM device minor number */
-
-   int               frontOffset;      /**< \brief Front color buffer offset */
-   int               frontPitch;       /**< \brief Front color buffer pitch */
-   int               backOffset;       /**< \brief Back color buffer offset */
-   int               backPitch;        /**< \brief Back color buffer pitch */
-   int               depthOffset;      /**< \brief Depth buffer offset */
-   int               depthPitch;       /**< \brief Depth buffer pitch */
-   int               textureOffset;    /**< \brief Texture area offset */
-   int               textureSize;      /**< \brief Texture area size */
-   int               log2TexGran;      /**< \brief Texture granularity in base 2 log */
-
-   unsigned int      frontPitchOffset;
-   unsigned int      backPitchOffset;
-   unsigned int      depthPitchOffset;
-   
-   int               colorTiling;      /**< \brief Enable color tiling */
-
-   int               irq;              /**< \brief IRQ number */
-   int               page_flip_enable; /**< \brief Page Flip enable */
-   unsigned int      gen_int_cntl;
-   unsigned int      crtc_offset_cntl;
-
-   unsigned long     pcieGartTableOffset;
-} RADEONInfoRec, *RADEONInfoPtr;
-
-
-#endif /* _RADEON_H_ */
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_reg.h b/src/mesa/drivers/dri/radeon/server/radeon_reg.h
index 1b33de1edf7..7ba5b38c4cb 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_reg.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon_reg.h
@@ -777,8 +777,6 @@
 #       define RADEON_MEM_NUM_CHANNELS_MASK 0x01
 #       define RADEON_MEM_USE_B_CH_ONLY     (1<<1)
 #       define RV100_HALF_MODE              (1<<3)
-#       define R300_MEM_NUM_CHANNELS_MASK   0x03
-#       define R300_MEM_USE_CD_CH_ONLY      (1<<2)
 #define RADEON_MEM_TIMING_CNTL              0x0144 /* EXT_MEM_CNTL */
 #define RADEON_MEM_INIT_LAT_TIMER           0x0154
 #define RADEON_MEM_INTF_CNTL                0x014c
@@ -792,13 +790,6 @@
 #define RADEON_MPLL_CNTL                    0x000e /* PLL */
 #define RADEON_MPP_TB_CONFIG                0x01c0 /* ? */
 #define RADEON_MPP_GP_CONFIG                0x01c8 /* ? */
-#define R300_MC_IND_INDEX                   0x01f8
-#       define R300_MC_IND_ADDR_MASK        0x3f
-#define R300_MC_IND_DATA                    0x01fc
-#define R300_MC_READ_CNTL_AB                0x017c
-#       define R300_MEM_RBS_POSITION_A_MASK 0x03
-#define R300_MC_READ_CNTL_CD_mcind	    0x24
-#       define R300_MEM_RBS_POSITION_C_MASK 0x03
 
 #define RADEON_N_VIF_COUNT                  0x0248
 
@@ -954,8 +945,6 @@
 #       define RADEON_P2PLL_REF_DIV_MASK    0x03ff
 #       define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
 #       define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
-#       define R300_PPLL_REF_DIV_ACC_MASK   (0x3ff << 18)
-#       define R300_PPLL_REF_DIV_ACC_SHIFT  18
 #define RADEON_PALETTE_DATA                 0x00b4
 #define RADEON_PALETTE_30_DATA              0x00b8
 #define RADEON_PALETTE_INDEX                0x00b0