diff options
| author | Samuel Pitoiset <[email protected]> | 2017-12-07 11:39:46 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2017-12-08 11:15:44 +0100 |
| commit | fc6c77e162df3405e6de9f5644788984b2f7aacc (patch) | |
| tree | cb3d31417a758756cfb5070cc8b91f7257ab96fd | |
| parent | 4d81c8e43e2b235684e480da02eab2c647e6de6b (diff) | |
radv: fix TC-compat HTILE with VK_FORMAT_D32_SFLOAT_S8_UINT on Vega
Copied from RadeonSI.
This fixes all CTS
dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.clear.*
And some other ones which use the same format.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 5c53e816376..efd17e48896 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -416,6 +416,12 @@ si_make_texture_descriptor(struct radv_device *device, data_format = 0; } + /* S8 with Z32 HTILE needs a special format. */ + if (device->physical_device->rad_info.chip_class >= GFX9 && + vk_format == VK_FORMAT_S8_UINT && + image->tc_compatible_htile) + data_format = V_008F14_IMG_DATA_FORMAT_S8_32; + type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples, is_storage_image, device->physical_device->rad_info.chip_class >= GFX9); if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) { |