diff options
author | Jason Ekstrand <[email protected]> | 2017-05-17 11:54:24 -0700 |
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committer | Jason Ekstrand <[email protected]> | 2017-05-23 17:37:43 -0700 |
commit | 39adea9330376a64a4b5e8da98f5e055ebd3331e (patch) | |
tree | 6f3ab8cbee789721bdf99f20ecfeb770733a7b4b | |
parent | 50d0eb5096bd9514821a641f25c0b3455c0f8a88 (diff) |
anv: Require vertex buffers to come from a 32-bit heap
Reviewed-by: Nanley Chery <[email protected]>
Cc: "17.1" <[email protected]>
-rw-r--r-- | src/intel/vulkan/anv_device.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index ab7726fb93d..ab484ed0f9a 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -153,6 +153,18 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd) for (uint32_t heap = 0; heap < device->memory.heap_count; heap++) { uint32_t valid_buffer_usage = ~0; + /* There appears to be a hardware issue in the VF cache where it only + * considers the bottom 32 bits of memory addresses. If you happen to + * have two vertex buffers which get placed exactly 4 GiB apart and use + * them in back-to-back draw calls, you can get collisions. In order to + * solve this problem, we require vertex and index buffers be bound to + * memory allocated out of the 32-bit heap. + */ + if (device->memory.heaps[heap].supports_48bit_addresses) { + valid_buffer_usage &= ~(VK_BUFFER_USAGE_INDEX_BUFFER_BIT | + VK_BUFFER_USAGE_VERTEX_BUFFER_BIT); + } + if (device->info.has_llc) { /* Big core GPUs share LLC with the CPU and thus one memory type can be * both cached and coherent at the same time. |