diff options
| author | Dave Airlie <[email protected]> | 2015-02-18 23:51:19 +0000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2015-12-01 12:57:55 +1000 |
| commit | 8168dfdd4e63457bd8a9ef04a5d49a1f2e202ab8 (patch) | |
| tree | 529dd85c4be13b442aa72cce269e116ea23b9985 | |
| parent | 2ab9cd0c4dcefb3e63266cadc1e06079e67c3962 (diff) | |
r600: geometry shader gsvs itemsize workaround
On some chips the GSVS itemsize needs to be aligned to a cacheline size.
This only applies to some of the r600 family chips.
Reviewed-by: Marek Olšák <[email protected]>
Cc: "10.6 11.0 11.1" <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
| -rw-r--r-- | src/gallium/drivers/r600/r600_state.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index c2d4abc5ea1..c59e6c0183b 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -2675,6 +2675,9 @@ void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *sha S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport); } +#define RV610_GSVS_ALIGN 32 +#define R600_GSVS_ALIGN 16 + void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) { struct r600_context *rctx = (struct r600_context *)ctx; @@ -2684,6 +2687,23 @@ void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *sha unsigned gsvs_itemsize = (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2; + /* some r600s needs gsvs itemsize aligned to cacheline size + this was fixed in rs780 and above. */ + switch (rctx->b.family) { + case CHIP_RV610: + gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN); + break; + case CHIP_R600: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN); + break; + default: + break; + } + r600_init_command_buffer(cb, 64); /* VGT_GS_MODE is written by r600_emit_shader_stages */ |