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authorEric Anholt <[email protected]>2010-05-04 11:47:57 -0700
committerEric Anholt <[email protected]>2010-06-24 15:05:19 -0700
commit7aa0b034f70e3140aece94091b2ab200427077e9 (patch)
tree939e81e2bc2cc51cb9330d421a04baa4882ac730
parentf14913d4b7ede498803615296651cab4bbd341d7 (diff)
ir_to_mesa: Fix up the assign rule to use left and right correctly.
The destination of assign is in left, not in the node itself.
-rw-r--r--mesa_codegen.brg4
1 files changed, 2 insertions, 2 deletions
diff --git a/mesa_codegen.brg b/mesa_codegen.brg
index 6a34b68068e..9f2761b08e2 100644
--- a/mesa_codegen.brg
+++ b/mesa_codegen.brg
@@ -120,8 +120,8 @@ alloced_vec4: vec4 1
stmt: assign(alloced_vec4, alloced_vec4) 1
{
ir_to_mesa_emit_op1(tree, OPCODE_MOV,
- ir_to_mesa_dst_reg_from_src(tree->src_reg),
- tree->left->src_reg);
+ ir_to_mesa_dst_reg_from_src(tree->left->src_reg),
+ tree->right->src_reg);
}
# Perform a swizzle by composing our swizzle with the swizzle