diff options
author | Ilia Mirkin <imirkin@alum.mit.edu> | 2017-11-19 15:13:41 -0500 |
---|---|---|
committer | Ilia Mirkin <imirkin@alum.mit.edu> | 2017-11-25 17:20:17 -0500 |
commit | ffdcd51e660358badf76bd055025e8405ae374bb (patch) | |
tree | 400f0fd70a5a68c43cb7fb9a7bd7f1525d236c7b | |
parent | 86f12e9377374108474b6a5d6b5dd6e9d37766db (diff) |
freedreno/a4xx: add stencil texturing support
Copied from a5xx, should be identical.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@gmail.com>
-rw-r--r-- | docs/features.txt | 6 | ||||
-rw-r--r-- | src/gallium/drivers/freedreno/a4xx/fd4_emit.c | 2 | ||||
-rw-r--r-- | src/gallium/drivers/freedreno/a4xx/fd4_format.c | 11 | ||||
-rw-r--r-- | src/gallium/drivers/freedreno/a4xx/fd4_texture.c | 34 |
4 files changed, 38 insertions, 15 deletions
diff --git a/docs/features.txt b/docs/features.txt index 7f9a18ddd79..e4eac28a917 100644 --- a/docs/features.txt +++ b/docs/features.txt @@ -180,7 +180,7 @@ GL 4.3, GLSL 4.30 -- all DONE: i965/gen8+, nvc0, radeonsi GL_ARB_robust_buffer_access_behavior DONE (i965) GL_ARB_shader_image_size DONE (freedreno/a5xx, i965, r600, softpipe) GL_ARB_shader_storage_buffer_object DONE (freedreno/a5xx, i965, softpipe) - GL_ARB_stencil_texturing DONE (freedreno/a5xx, i965/hsw+, nv50, r600, llvmpipe, softpipe, swr) + GL_ARB_stencil_texturing DONE (freedreno, i965/hsw+, nv50, r600, llvmpipe, softpipe, swr) GL_ARB_texture_buffer_range DONE (freedreno, nv50, i965, r600, llvmpipe) GL_ARB_texture_query_levels DONE (all drivers that support GLSL 1.30) GL_ARB_texture_storage_multisample DONE (all drivers that support GL_ARB_texture_multisample) @@ -203,7 +203,7 @@ GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+, nvc0, radeonsi GL_ARB_multi_bind DONE (all drivers) GL_ARB_query_buffer_object DONE (i965/hsw+) GL_ARB_texture_mirror_clamp_to_edge DONE (i965, nv50, r600, llvmpipe, softpipe, swr) - GL_ARB_texture_stencil8 DONE (freedreno/a5xx, i965/hsw+, nv50, r600, llvmpipe, softpipe, swr) + GL_ARB_texture_stencil8 DONE (freedreno, i965/hsw+, nv50, r600, llvmpipe, softpipe, swr) GL_ARB_vertex_type_10f_11f_11f_rev DONE (i965, nv50, r600, llvmpipe, softpipe, swr) GL 4.5, GLSL 4.50 -- all DONE: nvc0, radeonsi @@ -252,7 +252,7 @@ GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, radeonsi GL_ARB_shader_storage_buffer_object DONE (freedreno/a5xx, i965/gen7+, softpipe) GL_ARB_shading_language_packing DONE (all drivers) GL_ARB_separate_shader_objects DONE (all drivers) - GL_ARB_stencil_texturing DONE (freedreno/a5xx, nv50, r600, llvmpipe, softpipe, swr) + GL_ARB_stencil_texturing DONE (freedreno, nv50, r600, llvmpipe, softpipe, swr) GL_ARB_texture_multisample (Multisample textures) DONE (i965/gen7+, nv50, r600, llvmpipe, softpipe) GL_ARB_texture_storage_multisample DONE (all drivers that support GL_ARB_texture_multisample) GL_ARB_vertex_attrib_binding DONE (all drivers) diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c index 0f7c6470330..8262b45daad 100644 --- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c +++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c @@ -190,6 +190,8 @@ emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring, OUT_RING(ring, view->texconst3); if (view->base.texture) { struct fd_resource *rsc = fd_resource(view->base.texture); + if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT) + rsc = rsc->stencil; OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0); } else { OUT_RING(ring, 0x00000000); diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_format.c b/src/gallium/drivers/freedreno/a4xx/fd4_format.c index 3e1dc277850..83fd9338077 100644 --- a/src/gallium/drivers/freedreno/a4xx/fd4_format.c +++ b/src/gallium/drivers/freedreno/a4xx/fd4_format.c @@ -211,10 +211,13 @@ static struct fd4_format formats[PIPE_FORMAT_COUNT] = { VT(R11G11B10_FLOAT, 11_11_10_FLOAT, R11G11B10_FLOAT, WZYX), _T(R9G9B9E5_FLOAT, 9_9_9_E5_FLOAT, NONE, WZYX), - _T(Z24X8_UNORM, X8Z24_UNORM, R8G8B8A8_UNORM, WZYX), - _T(Z24_UNORM_S8_UINT, X8Z24_UNORM, R8G8B8A8_UNORM, WZYX), - _T(Z32_FLOAT, 32_FLOAT, R8G8B8A8_UNORM, WZYX), - _T(Z32_FLOAT_S8X24_UINT, 32_FLOAT,R8G8B8A8_UNORM, WZYX), + _T(Z16_UNORM, 16_UNORM, R8G8_UNORM, WZYX), + _T(Z24X8_UNORM, X8Z24_UNORM, R8G8B8A8_UNORM, WZYX), + _T(X24S8_UINT, 8_8_8_8_UINT, R8G8B8A8_UINT, XYZW), + _T(Z24_UNORM_S8_UINT, X8Z24_UNORM, R8G8B8A8_UNORM, WZYX), + _T(Z32_FLOAT, 32_FLOAT, R8G8B8A8_UNORM, WZYX), + _T(Z32_FLOAT_S8X24_UINT, 32_FLOAT, R8G8B8A8_UNORM, WZYX), + _T(X32_S8X24_UINT, 8_UINT, R8_UINT, WZYX), /* 48-bit */ V_(R16G16B16_UNORM, 16_16_16_UNORM, NONE, WZYX), diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c index 4faeceee5e6..4b2ca463458 100644 --- a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c +++ b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c @@ -224,12 +224,18 @@ fd4_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc, { struct fd4_pipe_sampler_view *so = CALLOC_STRUCT(fd4_pipe_sampler_view); struct fd_resource *rsc = fd_resource(prsc); + enum pipe_format format = cso->format; unsigned lvl, layers; uint32_t sz2 = 0; if (!so) return NULL; + if (format == PIPE_FORMAT_X32_S8X24_UINT) { + rsc = rsc->stencil; + format = rsc->base.b.format; + } + so->base = *cso; pipe_reference(NULL, &prsc->reference); so->base.texture = prsc; @@ -238,25 +244,25 @@ fd4_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc, so->texconst0 = A4XX_TEX_CONST_0_TYPE(tex_type(cso->target)) | - A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(cso->format)) | - fd4_tex_swiz(cso->format, cso->swizzle_r, cso->swizzle_g, + A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) | + fd4_tex_swiz(format, cso->swizzle_r, cso->swizzle_g, cso->swizzle_b, cso->swizzle_a); - if (util_format_is_srgb(cso->format)) { - if (use_astc_srgb_workaround(pctx, cso->format)) + if (util_format_is_srgb(format)) { + if (use_astc_srgb_workaround(pctx, format)) so->astc_srgb = true; so->texconst0 |= A4XX_TEX_CONST_0_SRGB; } if (cso->target == PIPE_BUFFER) { - unsigned elements = cso->u.buf.size / util_format_get_blocksize(cso->format); + unsigned elements = cso->u.buf.size / util_format_get_blocksize(format); lvl = 0; so->texconst1 = A4XX_TEX_CONST_1_WIDTH(elements) | A4XX_TEX_CONST_1_HEIGHT(1); so->texconst2 = - A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(cso->format)) | + A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)) | A4XX_TEX_CONST_2_PITCH(elements * rsc->cpp); so->offset = cso->u.buf.offset; } else { @@ -271,13 +277,25 @@ fd4_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc, A4XX_TEX_CONST_1_WIDTH(u_minify(prsc->width0, lvl)) | A4XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl)); so->texconst2 = - A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(cso->format)) | + A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)) | A4XX_TEX_CONST_2_PITCH( util_format_get_nblocksx( - cso->format, rsc->slices[lvl].pitch) * rsc->cpp); + format, rsc->slices[lvl].pitch) * rsc->cpp); so->offset = fd_resource_offset(rsc, lvl, cso->u.tex.first_layer); } + /* NOTE: since we sample z24s8 using 8888_UINT format, the swizzle + * we get isn't quite right. Use SWAP(XYZW) as a cheap and cheerful + * way to re-arrange things so stencil component is where the swiz + * expects. + * + * Note that gallium expects stencil sampler to return (s,s,s,s) + * which isn't quite true. To make that happen we'd have to massage + * the swizzle. But in practice only the .x component is used. + */ + if (format == PIPE_FORMAT_X24S8_UINT) + so->texconst2 |= A4XX_TEX_CONST_2_SWAP(XYZW); + switch (cso->target) { case PIPE_TEXTURE_1D_ARRAY: case PIPE_TEXTURE_2D_ARRAY: |