Merge remote-tracking branch 'mesa-public/master' into vulkan

This pulls in a shared local memory fix.

18 files changed, 652 insertions, 71 deletions

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index 7a2f43b1fe8..ac910525082 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -151,6 +151,8 @@ i965_FILES = \
 	brw_state.h \
 	brw_state_upload.c \
 	brw_structs.h \
+	brw_tcs_surface_state.c \
+	brw_tes_surface_state.c \
 	brw_tex.c \
 	brw_tex_layout.c \
 	brw_urb.c \
diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c
index d8226e0ca05..80935cf0aae 100644
--- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
+++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
@@ -196,6 +196,60 @@ const struct brw_tracked_state brw_wm_binding_table = {
    .emit = brw_upload_wm_binding_table,
 };
 
+/** Upload the TCS binding table (if TCS is active). */
+static void
+brw_tcs_upload_binding_table(struct brw_context *brw)
+{
+   /* If there's no TCS, skip changing anything. */
+   if (brw->tess_ctrl_program == NULL)
+      return;
+
+   /* BRW_NEW_TCS_PROG_DATA */
+   const struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data;
+   brw_upload_binding_table(brw,
+                            _3DSTATE_BINDING_TABLE_POINTERS_HS,
+                            prog_data,
+                            &brw->tcs.base);
+}
+
+const struct brw_tracked_state brw_tcs_binding_table = {
+   .dirty = {
+      .mesa = 0,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_SURFACES |
+             BRW_NEW_TCS_CONSTBUF |
+             BRW_NEW_TCS_PROG_DATA,
+   },
+   .emit = brw_tcs_upload_binding_table,
+};
+
+/** Upload the TES binding table (if TES is active). */
+static void
+brw_tes_upload_binding_table(struct brw_context *brw)
+{
+   /* If there's no TES, skip changing anything. */
+   if (brw->tess_eval_program == NULL)
+      return;
+
+   /* BRW_NEW_TES_PROG_DATA */
+   const struct brw_stage_prog_data *prog_data = brw->tes.base.prog_data;
+   brw_upload_binding_table(brw,
+                            _3DSTATE_BINDING_TABLE_POINTERS_DS,
+                            prog_data,
+                            &brw->tes.base);
+}
+
+const struct brw_tracked_state brw_tes_binding_table = {
+   .dirty = {
+      .mesa = 0,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_SURFACES |
+             BRW_NEW_TES_CONSTBUF |
+             BRW_NEW_TES_PROG_DATA,
+   },
+   .emit = brw_tes_upload_binding_table,
+};
+
 /** Upload the GS binding table (if GS is active). */
 static void
 brw_gs_upload_binding_table(struct brw_context *brw)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index a8455413e36..1cc4c7b1282 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -195,6 +195,8 @@ enum brw_state_id {
    BRW_STATE_BATCH,
    BRW_STATE_INDEX_BUFFER,
    BRW_STATE_VS_CONSTBUF,
+   BRW_STATE_TCS_CONSTBUF,
+   BRW_STATE_TES_CONSTBUF,
    BRW_STATE_GS_CONSTBUF,
    BRW_STATE_PROGRAM_CACHE,
    BRW_STATE_STATE_BASE_ADDRESS,
@@ -281,6 +283,8 @@ enum brw_state_id {
 /** \see brw.state.depth_region */
 #define BRW_NEW_INDEX_BUFFER            (1ull << BRW_STATE_INDEX_BUFFER)
 #define BRW_NEW_VS_CONSTBUF             (1ull << BRW_STATE_VS_CONSTBUF)
+#define BRW_NEW_TCS_CONSTBUF            (1ull << BRW_STATE_TCS_CONSTBUF)
+#define BRW_NEW_TES_CONSTBUF            (1ull << BRW_STATE_TES_CONSTBUF)
 #define BRW_NEW_GS_CONSTBUF             (1ull << BRW_STATE_GS_CONSTBUF)
 #define BRW_NEW_PROGRAM_CACHE           (1ull << BRW_STATE_PROGRAM_CACHE)
 #define BRW_NEW_STATE_BASE_ADDRESS      (1ull << BRW_STATE_STATE_BASE_ADDRESS)
@@ -1232,7 +1236,7 @@ struct brw_context
    } perfmon;
 
    int num_atoms[BRW_NUM_PIPELINES];
-   const struct brw_tracked_state render_atoms[62];
+   const struct brw_tracked_state render_atoms[76];
    const struct brw_tracked_state compute_atoms[10];
 
    /* If (INTEL_DEBUG & DEBUG_BATCH) */
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 686b42be11e..08ad63ade9f 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -204,6 +204,14 @@ void brw_set_sampler_message(struct brw_codegen *p,
                              unsigned simd_mode,
                              unsigned return_format);
 
+void brw_set_message_descriptor(struct brw_codegen *p,
+                                brw_inst *inst,
+                                enum brw_message_target sfid,
+                                unsigned msg_length,
+                                unsigned response_length,
+                                bool header_present,
+                                bool end_of_thread);
+
 void brw_set_dp_read_message(struct brw_codegen *p,
 			     brw_inst *insn,
 			     unsigned binding_table_index,
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 25064c0eb87..5fb96626649 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -534,7 +534,7 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
  *       \b before filling out any message-specific data.  Callers can
  *       choose not to fill in irrelevant bits; they will be zero.
  */
-static void
+void
 brw_set_message_descriptor(struct brw_codegen *p,
 			   brw_inst *inst,
 			   enum brw_message_target sfid,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index fdf2f5be2a6..c52bc04c8ca 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2453,7 +2453,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
 
       /* Get the offset to read from */
       fs_reg offset_reg;
-      nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
+      nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
       if (const_offset) {
          offset_reg = brw_imm_ud(instr->const_index[0] + const_offset->u[0]);
       } else {
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 76f0185fdd7..790f1009ca7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -700,6 +700,9 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
    const struct brw_vue_map *vue_map = &vue_prog_data->vue_map;
    bool flush;
    fs_reg sources[8];
+   fs_reg urb_handle;
+
+   urb_handle = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
 
    /* If we don't have any valid slots to write, just do a minimal urb write
     * send to terminate the shader.  This includes 1 slot of undefined data,
@@ -713,8 +716,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
     */
    if (vue_map->slots_valid == 0) {
       fs_reg payload = fs_reg(VGRF, alloc.allocate(2), BRW_REGISTER_TYPE_UD);
-      bld.exec_all().MOV(payload, fs_reg(retype(brw_vec8_grf(1, 0),
-                                                BRW_REGISTER_TYPE_UD)));
+      bld.exec_all().MOV(payload, urb_handle);
 
       fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_SIMD8, reg_undef, payload);
       inst->eot = true;
@@ -858,8 +860,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
             ralloc_array(mem_ctx, fs_reg, length + header_size);
          fs_reg payload = fs_reg(VGRF, alloc.allocate(length + header_size),
                                  BRW_REGISTER_TYPE_F);
-         payload_sources[0] =
-            fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
+         payload_sources[0] = urb_handle;
 
          if (opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT)
             payload_sources[1] = per_slot_offsets;
@@ -871,7 +872,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
                            header_size);
 
          fs_inst *inst = abld.emit(opcode, reg_undef, payload);
-         inst->eot = last && stage == MESA_SHADER_VERTEX;
+         inst->eot = last && stage != MESA_SHADER_GEOMETRY;
          inst->mlen = length + header_size;
          inst->offset = urb_offset;
          urb_offset = starting_urb_offset + slot + 1;
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index 6d73444dad0..3f29e2fc105 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -55,6 +55,8 @@ gen7_emit_sampler_state_pointers_xs(struct brw_context *brw,
 {
    static const uint16_t packet_headers[] = {
       [MESA_SHADER_VERTEX] = _3DSTATE_SAMPLER_STATE_POINTERS_VS,
+      [MESA_SHADER_TESS_CTRL] = _3DSTATE_SAMPLER_STATE_POINTERS_HS,
+      [MESA_SHADER_TESS_EVAL] = _3DSTATE_SAMPLER_STATE_POINTERS_DS,
       [MESA_SHADER_GEOMETRY] = _3DSTATE_SAMPLER_STATE_POINTERS_GS,
       [MESA_SHADER_FRAGMENT] = _3DSTATE_SAMPLER_STATE_POINTERS_PS,
    };
@@ -647,3 +649,47 @@ const struct brw_tracked_state brw_gs_samplers = {
    },
    .emit = brw_upload_gs_samplers,
 };
+
+
+static void
+brw_upload_tcs_samplers(struct brw_context *brw)
+{
+   /* BRW_NEW_TESS_CTRL_PROGRAM */
+   struct gl_program *tcs = (struct gl_program *) brw->tess_ctrl_program;
+   if (!tcs)
+      return;
+
+   brw_upload_sampler_state_table(brw, tcs, &brw->tcs.base);
+}
+
+
+const struct brw_tracked_state brw_tcs_samplers = {
+   .dirty = {
+      .mesa = _NEW_TEXTURE,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_TESS_CTRL_PROGRAM,
+   },
+   .emit = brw_upload_tcs_samplers,
+};
+
+
+static void
+brw_upload_tes_samplers(struct brw_context *brw)
+{
+   /* BRW_NEW_TESS_EVAL_PROGRAM */
+   struct gl_program *tes = (struct gl_program *) brw->tess_eval_program;
+   if (!tes)
+      return;
+
+   brw_upload_sampler_state_table(brw, tes, &brw->tes.base);
+}
+
+
+const struct brw_tracked_state brw_tes_samplers = {
+   .dirty = {
+      .mesa = _NEW_TEXTURE,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_TESS_EVAL_PROGRAM,
+   },
+   .emit = brw_upload_tes_samplers,
+};
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 59acec990be..d29b997b963 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -47,6 +47,8 @@ extern const struct brw_tracked_state brw_cc_unit;
 extern const struct brw_tracked_state brw_clip_prog;
 extern const struct brw_tracked_state brw_clip_unit;
 extern const struct brw_tracked_state brw_vs_pull_constants;
+extern const struct brw_tracked_state brw_tcs_pull_constants;
+extern const struct brw_tracked_state brw_tes_pull_constants;
 extern const struct brw_tracked_state brw_gs_pull_constants;
 extern const struct brw_tracked_state brw_wm_pull_constants;
 extern const struct brw_tracked_state brw_cs_pull_constants;
@@ -70,20 +72,32 @@ extern const struct brw_tracked_state brw_state_base_address;
 extern const struct brw_tracked_state brw_urb_fence;
 extern const struct brw_tracked_state brw_vs_prog;
 extern const struct brw_tracked_state brw_vs_samplers;
+extern const struct brw_tracked_state brw_tcs_samplers;
+extern const struct brw_tracked_state brw_tes_samplers;
 extern const struct brw_tracked_state brw_gs_samplers;
 extern const struct brw_tracked_state brw_vs_ubo_surfaces;
 extern const struct brw_tracked_state brw_vs_abo_surfaces;
 extern const struct brw_tracked_state brw_vs_image_surfaces;
+extern const struct brw_tracked_state brw_tcs_ubo_surfaces;
+extern const struct brw_tracked_state brw_tcs_abo_surfaces;
+extern const struct brw_tracked_state brw_tcs_image_surfaces;
+extern const struct brw_tracked_state brw_tes_ubo_surfaces;
+extern const struct brw_tracked_state brw_tes_abo_surfaces;
+extern const struct brw_tracked_state brw_tes_image_surfaces;
 extern const struct brw_tracked_state brw_gs_ubo_surfaces;
 extern const struct brw_tracked_state brw_gs_abo_surfaces;
 extern const struct brw_tracked_state brw_gs_image_surfaces;
 extern const struct brw_tracked_state brw_vs_unit;
+extern const struct brw_tracked_state brw_hs_prog;
+extern const struct brw_tracked_state brw_ds_prog;
 extern const struct brw_tracked_state brw_gs_prog;
 extern const struct brw_tracked_state brw_wm_prog;
 extern const struct brw_tracked_state brw_renderbuffer_surfaces;
 extern const struct brw_tracked_state brw_texture_surfaces;
 extern const struct brw_tracked_state brw_wm_binding_table;
 extern const struct brw_tracked_state brw_gs_binding_table;
+extern const struct brw_tracked_state brw_tes_binding_table;
+extern const struct brw_tracked_state brw_tcs_binding_table;
 extern const struct brw_tracked_state brw_vs_binding_table;
 extern const struct brw_tracked_state brw_wm_ubo_surfaces;
 extern const struct brw_tracked_state brw_wm_abo_surfaces;
@@ -129,6 +143,7 @@ extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_clip_state;
 extern const struct brw_tracked_state gen7_ds_state;
 extern const struct brw_tracked_state gen7_gs_state;
+extern const struct brw_tracked_state gen7_tcs_push_constants;
 extern const struct brw_tracked_state gen7_hs_state;
 extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_ps_state;
@@ -138,6 +153,7 @@ extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_sf_state;
 extern const struct brw_tracked_state gen7_sol_state;
 extern const struct brw_tracked_state gen7_te_state;
+extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state gen7_vs_state;
 extern const struct brw_tracked_state gen7_wm_state;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 76bf4024d41..cf3cf97daea 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -288,10 +288,14 @@ static const struct brw_tracked_state *gen8_render_atoms[] =
    &gen7_hw_binding_tables, /* Enable hw-generated binding tables for Broadwell */
 
    &brw_vs_image_surfaces, /* Before vs push/pull constants and binding table */
+   &brw_tcs_image_surfaces, /* Before tcs push/pull constants and binding table */
+   &brw_tes_image_surfaces, /* Before tes push/pull constants and binding table */
    &brw_gs_image_surfaces, /* Before gs push/pull constants and binding table */
    &brw_wm_image_surfaces, /* Before wm push/pull constants and binding table */
 
    &gen6_vs_push_constants, /* Before vs_state */
+   &gen7_tcs_push_constants,
+   &gen7_tes_push_constants,
    &gen6_gs_push_constants, /* Before gs_state */
    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 
@@ -301,6 +305,12 @@ static const struct brw_tracked_state *gen8_render_atoms[] =
    &brw_vs_pull_constants,
    &brw_vs_ubo_surfaces,
    &brw_vs_abo_surfaces,
+   &brw_tcs_pull_constants,
+   &brw_tcs_ubo_surfaces,
+   &brw_tcs_abo_surfaces,
+   &brw_tes_pull_constants,
+   &brw_tes_ubo_surfaces,
+   &brw_tes_abo_surfaces,
    &brw_gs_pull_constants,
    &brw_gs_ubo_surfaces,
    &brw_gs_abo_surfaces,
@@ -310,11 +320,15 @@ static const struct brw_tracked_state *gen8_render_atoms[] =
    &gen6_renderbuffer_surfaces,
    &brw_texture_surfaces,
    &brw_vs_binding_table,
+   &brw_tcs_binding_table,
+   &brw_tes_binding_table,
    &brw_gs_binding_table,
    &brw_wm_binding_table,
 
    &brw_fs_samplers,
    &brw_vs_samplers,
+   &brw_tcs_samplers,
+   &brw_tes_samplers,
    &brw_gs_samplers,
    &gen8_multisample_state,
 
@@ -609,6 +623,8 @@ static struct dirty_bit_map brw_bits[] = {
    DEFINE_BIT(BRW_NEW_BATCH),
    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
+   DEFINE_BIT(BRW_NEW_TCS_CONSTBUF),
+   DEFINE_BIT(BRW_NEW_TES_CONSTBUF),
    DEFINE_BIT(BRW_NEW_GS_CONSTBUF),
    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
diff --git a/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c b/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c
new file mode 100644
index 00000000000..115c5abd391
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "main/mtypes.h"
+#include "program/prog_parameter.h"
+
+#include "brw_context.h"
+#include "brw_state.h"
+
+
+/* Creates a new TCS constant buffer reflecting the current TCS program's
+ * constants, if needed by the TCS program.
+ *
+ * Otherwise, constants go through the CURBEs using the brw_constant_buffer
+ * state atom.
+ */
+static void
+brw_upload_tcs_pull_constants(struct brw_context *brw)
+{
+   struct brw_stage_state *stage_state = &brw->tcs.base;
+
+   /* BRW_NEW_TESS_CTRL_PROGRAM */
+   struct brw_tess_ctrl_program *tcp =
+      (struct brw_tess_ctrl_program *) brw->tess_ctrl_program;
+
+   if (!tcp)
+      return;
+
+   /* BRW_NEW_TCS_PROG_DATA */
+   const struct brw_stage_prog_data *prog_data = &brw->tcs.prog_data->base.base;
+
+   /* _NEW_PROGRAM_CONSTANTS */
+   brw_upload_pull_constants(brw, BRW_NEW_TCS_CONSTBUF, &tcp->program.Base,
+                             stage_state, prog_data);
+}
+
+const struct brw_tracked_state brw_tcs_pull_constants = {
+   .dirty = {
+      .mesa = _NEW_PROGRAM_CONSTANTS,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_TCS_PROG_DATA |
+             BRW_NEW_TESS_CTRL_PROGRAM,
+   },
+   .emit = brw_upload_tcs_pull_constants,
+};
+
+static void
+brw_upload_tcs_ubo_surfaces(struct brw_context *brw)
+{
+   struct gl_context *ctx = &brw->ctx;
+
+   /* _NEW_PROGRAM */
+   struct gl_shader_program *prog =
+      ctx->_Shader->CurrentProgram[MESA_SHADER_TESS_CTRL];
+
+   if (!prog)
+      return;
+
+   /* BRW_NEW_TCS_PROG_DATA */
+   struct brw_stage_prog_data *prog_data = &brw->tcs.prog_data->base.base;
+
+   brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_TESS_CTRL],
+			   &brw->tcs.base, prog_data);
+}
+
+const struct brw_tracked_state brw_tcs_ubo_surfaces = {
+   .dirty = {
+      .mesa = _NEW_PROGRAM,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_TCS_PROG_DATA |
+             BRW_NEW_UNIFORM_BUFFER,
+   },
+   .emit = brw_upload_tcs_ubo_surfaces,
+};
+
+static void
+brw_upload_tcs_abo_surfaces(struct brw_context *brw)
+{
+   struct gl_context *ctx = &brw->ctx;
+   /* _NEW_PROGRAM */
+   struct gl_shader_program *prog =
+      ctx->_Shader->CurrentProgram[MESA_SHADER_TESS_CTRL];
+
+   if (prog) {
+      /* BRW_NEW_TCS_PROG_DATA */
+      brw_upload_abo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_TESS_CTRL],
+                              &brw->tcs.base, &brw->tcs.prog_data->base.base);
+   }
+}
+
+const struct brw_tracked_state brw_tcs_abo_surfaces = {
+   .dirty = {
+      .mesa = _NEW_PROGRAM,
+      .brw = BRW_NEW_ATOMIC_BUFFER |
+             BRW_NEW_BATCH |
+             BRW_NEW_TCS_PROG_DATA,
+   },
+   .emit = brw_upload_tcs_abo_surfaces,
+};
+
+static void
+brw_upload_tcs_image_surfaces(struct brw_context *brw)
+{
+   struct gl_context *ctx = &brw->ctx;
+   /* BRW_NEW_TESS_CTRL_PROGRAM */
+   struct gl_shader_program *prog =
+      ctx->_Shader->CurrentProgram[MESA_SHADER_TESS_CTRL];
+
+   if (prog) {
+      /* BRW_NEW_TCS_PROG_DATA, BRW_NEW_IMAGE_UNITS */
+      brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_TESS_CTRL],
+                                &brw->tcs.base, &brw->tcs.prog_data->base.base);
+   }
+}
+
+const struct brw_tracked_state brw_tcs_image_surfaces = {
+   .dirty = {
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_TCS_PROG_DATA |
+             BRW_NEW_IMAGE_UNITS |
+             BRW_NEW_TESS_CTRL_PROGRAM,
+   },
+   .emit = brw_upload_tcs_image_surfaces,
+};
diff --git a/src/mesa/drivers/dri/i965/brw_tes_surface_state.c b/src/mesa/drivers/dri/i965/brw_tes_surface_state.c
new file mode 100644
index 00000000000..142bd5a3109
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_tes_surface_state.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "main/mtypes.h"
+#include "program/prog_parameter.h"
+
+#include "brw_context.h"
+#include "brw_state.h"
+
+
+/* Creates a new TES constant buffer reflecting the current TES program's
+ * constants, if needed by the TES program.
+ *
+ * Otherwise, constants go through the CURBEs using the brw_constant_buffer
+ * state atom.
+ */
+static void
+brw_upload_tes_pull_constants(struct brw_context *brw)
+{
+   struct brw_stage_state *stage_state = &brw->tes.base;
+
+   /* BRW_NEW_TESS_EVAL_PROGRAM */
+   struct brw_tess_eval_program *dp =
+      (struct brw_tess_eval_program *) brw->tess_eval_program;
+
+   if (!dp)
+      return;
+
+   /* BRW_NEW_TES_PROG_DATA */
+   const struct brw_stage_prog_data *prog_data = &brw->tes.prog_data->base.base;
+
+   /* _NEW_PROGRAM_CONSTANTS */
+   brw_upload_pull_constants(brw, BRW_NEW_TES_CONSTBUF, &dp->program.Base,
+                             stage_state, prog_data);
+}
+
+const struct brw_tracked_state brw_tes_pull_constants = {
+   .dirty = {
+      .mesa = _NEW_PROGRAM_CONSTANTS,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_TES_PROG_DATA |
+             BRW_NEW_TESS_EVAL_PROGRAM,
+   },
+   .emit = brw_upload_tes_pull_constants,
+};
+
+static void
+brw_upload_tes_ubo_surfaces(struct brw_context *brw)
+{
+   struct gl_context *ctx = &brw->ctx;
+
+   /* _NEW_PROGRAM */
+   struct gl_shader_program *prog =
+      ctx->_Shader->CurrentProgram[MESA_SHADER_TESS_EVAL];
+
+   if (!prog)
+      return;
+
+   /* BRW_NEW_TES_PROG_DATA */
+   struct brw_stage_prog_data *prog_data = &brw->tes.prog_data->base.base;
+
+   brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_TESS_EVAL],
+			   &brw->tes.base, prog_data);
+}
+
+const struct brw_tracked_state brw_tes_ubo_surfaces = {
+   .dirty = {
+      .mesa = _NEW_PROGRAM,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_TES_PROG_DATA |
+             BRW_NEW_UNIFORM_BUFFER,
+   },
+   .emit = brw_upload_tes_ubo_surfaces,
+};
+
+static void
+brw_upload_tes_abo_surfaces(struct brw_context *brw)
+{
+   struct gl_context *ctx = &brw->ctx;
+   /* _NEW_PROGRAM */
+   struct gl_shader_program *prog =
+      ctx->_Shader->CurrentProgram[MESA_SHADER_TESS_EVAL];
+
+   if (prog) {
+      /* BRW_NEW_TES_PROG_DATA */
+      brw_upload_abo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_TESS_EVAL],
+                              &brw->tes.base, &brw->tes.prog_data->base.base);
+   }
+}
+
+const struct brw_tracked_state brw_tes_abo_surfaces = {
+   .dirty = {
+      .mesa = _NEW_PROGRAM,
+      .brw = BRW_NEW_ATOMIC_BUFFER |
+             BRW_NEW_BATCH |
+             BRW_NEW_TES_PROG_DATA,
+   },
+   .emit = brw_upload_tes_abo_surfaces,
+};
+
+static void
+brw_upload_tes_image_surfaces(struct brw_context *brw)
+{
+   struct gl_context *ctx = &brw->ctx;
+   /* BRW_NEW_TESS_EVAL_PROGRAM */
+   struct gl_shader_program *prog =
+      ctx->_Shader->CurrentProgram[MESA_SHADER_TESS_EVAL];
+
+   if (prog) {
+      /* BRW_NEW_TES_PROG_DATA, BRW_NEW_IMAGE_UNITS */
+      brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_TESS_EVAL],
+                                &brw->tes.base, &brw->tes.prog_data->base.base);
+   }
+}
+
+const struct brw_tracked_state brw_tes_image_surfaces = {
+   .dirty = {
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_IMAGE_UNITS |
+             BRW_NEW_TESS_EVAL_PROGRAM |
+             BRW_NEW_TES_PROG_DATA,
+   },
+   .emit = brw_upload_tes_image_surfaces,
+};
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 909db324aec..c4ebbf3b48c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -862,6 +862,12 @@ brw_update_texture_surfaces(struct brw_context *brw)
    /* BRW_NEW_VERTEX_PROGRAM */
    struct gl_program *vs = (struct gl_program *) brw->vertex_program;
 
+   /* BRW_NEW_TESS_CTRL_PROGRAM */
+   struct gl_program *tcs = (struct gl_program *) brw->tess_ctrl_program;
+
+   /* BRW_NEW_TESS_EVAL_PROGRAM */
+   struct gl_program *tes = (struct gl_program *) brw->tess_eval_program;
+
    /* BRW_NEW_GEOMETRY_PROGRAM */
    struct gl_program *gs = (struct gl_program *) brw->geometry_program;
 
@@ -873,6 +879,8 @@ brw_update_texture_surfaces(struct brw_context *brw)
 
    /* _NEW_TEXTURE */
    update_stage_texture_surfaces(brw, vs, &brw->vs.base, false);
+   update_stage_texture_surfaces(brw, tcs, &brw->tcs.base, false);
+   update_stage_texture_surfaces(brw, tes, &brw->tes.base, false);
    update_stage_texture_surfaces(brw, gs, &brw->gs.base, false);
    update_stage_texture_surfaces(brw, fs, &brw->wm.base, false);
    update_stage_texture_surfaces(brw, cs, &brw->cs.base, false);
@@ -883,6 +891,10 @@ brw_update_texture_surfaces(struct brw_context *brw)
    if (brw->gen < 8) {
       if (vs && vs->UsesGather)
          update_stage_texture_surfaces(brw, vs, &brw->vs.base, true);
+      if (tcs && tcs->UsesGather)
+         update_stage_texture_surfaces(brw, tcs, &brw->tcs.base, true);
+      if (tes && tes->UsesGather)
+         update_stage_texture_surfaces(brw, tes, &brw->tes.base, true);
       if (gs && gs->UsesGather)
          update_stage_texture_surfaces(brw, gs, &brw->gs.base, true);
       if (fs && fs->UsesGather)
@@ -903,6 +915,10 @@ const struct brw_tracked_state brw_texture_surfaces = {
              BRW_NEW_FS_PROG_DATA |
              BRW_NEW_GEOMETRY_PROGRAM |
              BRW_NEW_GS_PROG_DATA |
+             BRW_NEW_TESS_CTRL_PROGRAM |
+             BRW_NEW_TESS_EVAL_PROGRAM |
+             BRW_NEW_TCS_PROG_DATA |
+             BRW_NEW_TES_PROG_DATA |
              BRW_NEW_TEXTURE_BUFFER |
              BRW_NEW_VERTEX_PROGRAM |
              BRW_NEW_VS_PROG_DATA,
diff --git a/src/mesa/drivers/dri/i965/gen7_ds_state.c b/src/mesa/drivers/dri/i965/gen7_ds_state.c
index 79993b6d9f0..4d3d94f68a6 100644
--- a/src/mesa/drivers/dri/i965/gen7_ds_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_ds_state.c
@@ -27,6 +27,35 @@
 #include "intel_batchbuffer.h"
 
 static void
+gen7_upload_tes_push_constants(struct brw_context *brw)
+{
+   struct brw_stage_state *stage_state = &brw->tes.base;
+   /* BRW_NEW_TESS_EVAL_PROGRAM */
+   const struct brw_tess_eval_program *tep =
+      (struct brw_tess_eval_program *) brw->tess_eval_program;
+
+   if (tep) {
+      /* BRW_NEW_TES_PROG_DATA */
+      const struct brw_stage_prog_data *prog_data = &brw->tes.prog_data->base.base;
+      gen6_upload_push_constants(brw, &tep->program.Base, prog_data,
+                                      stage_state, AUB_TRACE_VS_CONSTANTS);
+   }
+
+   gen7_upload_constant_state(brw, stage_state, tep, _3DSTATE_CONSTANT_DS);
+}
+
+const struct brw_tracked_state gen7_tes_push_constants = {
+   .dirty = {
+      .mesa  = _NEW_PROGRAM_CONSTANTS,
+      .brw   = BRW_NEW_BATCH |
+               BRW_NEW_PUSH_CONSTANT_ALLOCATION |
+               BRW_NEW_TESS_EVAL_PROGRAM |
+               BRW_NEW_TES_PROG_DATA,
+   },
+   .emit = gen7_upload_tes_push_constants,
+};
+
+static void
 gen7_upload_ds_state(struct brw_context *brw)
 {
    /* Disable the DS Unit */
diff --git a/src/mesa/drivers/dri/i965/gen7_hs_state.c b/src/mesa/drivers/dri/i965/gen7_hs_state.c
index ae55f340f52..fcaa9197857 100644
--- a/src/mesa/drivers/dri/i965/gen7_hs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_hs_state.c
@@ -27,6 +27,35 @@
 #include "intel_batchbuffer.h"
 
 static void
+gen7_upload_tcs_push_constants(struct brw_context *brw)
+{
+   struct brw_stage_state *stage_state = &brw->tcs.base;
+   /* BRW_NEW_TESS_CTRL_PROGRAM */
+   const struct brw_tess_ctrl_program *tcp =
+      (struct brw_tess_ctrl_program *) brw->tess_ctrl_program;
+
+   if (tcp) {
+      /* BRW_NEW_TCS_PROG_DATA */
+      const struct brw_stage_prog_data *prog_data = &brw->tcs.prog_data->base.base;
+      gen6_upload_push_constants(brw, &tcp->program.Base, prog_data,
+                                      stage_state, AUB_TRACE_VS_CONSTANTS);
+   }
+
+   gen7_upload_constant_state(brw, stage_state, tcp, _3DSTATE_CONSTANT_HS);
+}
+
+const struct brw_tracked_state gen7_tcs_push_constants = {
+   .dirty = {
+      .mesa  = _NEW_PROGRAM_CONSTANTS,
+      .brw   = BRW_NEW_BATCH |
+               BRW_NEW_PUSH_CONSTANT_ALLOCATION |
+               BRW_NEW_TESS_CTRL_PROGRAM |
+               BRW_NEW_TCS_PROG_DATA,
+   },
+   .emit = gen7_upload_tcs_push_constants,
+};
+
+static void
 gen7_upload_hs_state(struct brw_context *brw)
 {
    /* Disable the HS Unit */
diff --git a/src/mesa/drivers/dri/i965/gen7_te_state.c b/src/mesa/drivers/dri/i965/gen7_te_state.c
index 95a5e98133b..2650fa562ec 100644
--- a/src/mesa/drivers/dri/i965/gen7_te_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_te_state.c
@@ -29,19 +29,39 @@
 static void
 upload_te_state(struct brw_context *brw)
 {
-   /* Disable the TE */
-   BEGIN_BATCH(4);
-   OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
+   /* BRW_NEW_TESS_EVAL_PROGRAM */
+   bool active = brw->tess_eval_program;
+   if (active)
+      assert(brw->tess_ctrl_program);
+
+   const struct brw_tes_prog_data *tes_prog_data = brw->tes.prog_data;
+
+   if (active) {
+      BEGIN_BATCH(4);
+      OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
+      OUT_BATCH((tes_prog_data->partitioning << GEN7_TE_PARTITIONING_SHIFT) |
+                (tes_prog_data->output_topology << GEN7_TE_OUTPUT_TOPOLOGY_SHIFT) |
+                (tes_prog_data->domain << GEN7_TE_DOMAIN_SHIFT) |
+                GEN7_TE_ENABLE);
+      OUT_BATCH_F(63.0);
+      OUT_BATCH_F(64.0);
+      ADVANCE_BATCH();
+   } else {
+      BEGIN_BATCH(4);
+      OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
+      OUT_BATCH(0);
+      OUT_BATCH_F(0);
+      OUT_BATCH_F(0);
+      ADVANCE_BATCH();
+   }
 }
 
 const struct brw_tracked_state gen7_te_state = {
    .dirty = {
       .mesa  = 0,
-      .brw   = BRW_NEW_CONTEXT,
+      .brw   = BRW_NEW_CONTEXT |
+               BRW_NEW_TES_PROG_DATA |
+               BRW_NEW_TESS_EVAL_PROGRAM,
    },
    .emit = upload_te_state,
 };
diff --git a/src/mesa/drivers/dri/i965/gen8_ds_state.c b/src/mesa/drivers/dri/i965/gen8_ds_state.c
index 2c0a04de140..a79e8aa020e 100644
--- a/src/mesa/drivers/dri/i965/gen8_ds_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ds_state.c
@@ -29,38 +29,71 @@
 static void
 gen8_upload_ds_state(struct brw_context *brw)
 {
-   /* Disable the DS Unit */
-   BEGIN_BATCH(11);
-   OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (11 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
+   struct gl_context *ctx = &brw->ctx;
+   const struct brw_stage_state *stage_state = &brw->tes.base;
+   /* BRW_NEW_TESS_EVAL_PROGRAM */
+   bool active = brw->tess_eval_program;
+   assert(!active || brw->tess_ctrl_program);
 
-   int ds_pkt_len = brw->gen >= 9 ? 11 : 9;
-   BEGIN_BATCH(ds_pkt_len);
-   OUT_BATCH(_3DSTATE_DS << 16 | (ds_pkt_len - 2));
-   for (int i = 0; i < ds_pkt_len - 1; i++)
+   /* BRW_NEW_TES_PROG_DATA */
+   const struct brw_tes_prog_data *tes_prog_data = brw->tes.prog_data;
+   const struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base;
+   const struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
+
+   if (active) {
+      BEGIN_BATCH(9);
+      OUT_BATCH(_3DSTATE_DS << 16 | (9 - 2));
+      OUT_BATCH(stage_state->prog_offset);
       OUT_BATCH(0);
-   ADVANCE_BATCH();
+      OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
+                          GEN7_DS_SAMPLER_COUNT) |
+                SET_FIELD(prog_data->binding_table.size_bytes / 4,
+                          GEN7_DS_BINDING_TABLE_ENTRY_COUNT));
+      if (prog_data->total_scratch) {
+         OUT_RELOC64(stage_state->scratch_bo,
+                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+                     ffs(prog_data->total_scratch) - 11);
+      } else {
+         OUT_BATCH(0);
+         OUT_BATCH(0);
+      }
+      OUT_BATCH(SET_FIELD(prog_data->dispatch_grf_start_reg,
+                          GEN7_DS_DISPATCH_START_GRF) |
+                SET_FIELD(vue_prog_data->urb_read_length,
+                          GEN7_DS_URB_READ_LENGTH));
 
-   BEGIN_BATCH(2);
-   OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_DS << 16 | (2 - 2));
-   OUT_BATCH(brw->hw_bt_pool.next_offset);
-   ADVANCE_BATCH();
+      OUT_BATCH(GEN7_DS_ENABLE |
+                GEN7_DS_STATISTICS_ENABLE |
+                (brw->max_ds_threads - 1) << HSW_DS_MAX_THREADS_SHIFT |
+                (vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ?
+                 GEN7_DS_SIMD8_DISPATCH_ENABLE : 0) |
+                (tes_prog_data->domain == BRW_TESS_DOMAIN_TRI ?
+                 GEN7_DS_COMPUTE_W_COORDINATE_ENABLE : 0));
+      OUT_BATCH(SET_FIELD(ctx->Transform.ClipPlanesEnabled,
+                          GEN8_DS_USER_CLIP_DISTANCE));
+      ADVANCE_BATCH();
+   } else {
+      BEGIN_BATCH(9);
+      OUT_BATCH(_3DSTATE_DS << 16 | (9 - 2));
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+   }
+   brw->tes.enabled = active;
 }
 
 const struct brw_tracked_state gen8_ds_state = {
    .dirty = {
       .mesa  = 0,
-      .brw   = BRW_NEW_CONTEXT,
+      .brw   = BRW_NEW_BATCH |
+               BRW_NEW_TESS_EVAL_PROGRAM |
+               BRW_NEW_TES_PROG_DATA,
    },
    .emit = gen8_upload_ds_state,
 };
diff --git a/src/mesa/drivers/dri/i965/gen8_hs_state.c b/src/mesa/drivers/dri/i965/gen8_hs_state.c
index 13f70ef0a81..38e22359ffb 100644
--- a/src/mesa/drivers/dri/i965/gen8_hs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_hs_state.c
@@ -29,43 +29,62 @@
 static void
 gen8_upload_hs_state(struct brw_context *brw)
 {
-   /* Disable the HS Unit */
-   BEGIN_BATCH(11);
-   OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (11 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
+   const struct brw_stage_state *stage_state = &brw->tcs.base;
+   /* BRW_NEW_TESS_CTRL_PROGRAM */
+   bool active = brw->tess_ctrl_program;
+   assert(!active || brw->tess_eval_program);
+   /* BRW_NEW_HS_PROG_DATA */
+   const struct brw_vue_prog_data *prog_data = &brw->tcs.prog_data->base;
 
-   BEGIN_BATCH(9);
-   OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-
-   BEGIN_BATCH(2);
-   OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_HS << 16 | (2 - 2));
-   OUT_BATCH(brw->hw_bt_pool.next_offset);
-   ADVANCE_BATCH();
+   if (active) {
+      BEGIN_BATCH(9);
+      OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2));
+      OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
+                          GEN7_HS_SAMPLER_COUNT) |
+                SET_FIELD(prog_data->base.binding_table.size_bytes / 4,
+                          GEN7_HS_BINDING_TABLE_ENTRY_COUNT));
+      OUT_BATCH(GEN7_HS_ENABLE |
+                GEN7_HS_STATISTICS_ENABLE |
+                (brw->max_hs_threads - 1) << GEN8_HS_MAX_THREADS_SHIFT |
+                SET_FIELD(brw->tcs.prog_data->instances - 1,
+                          GEN7_HS_INSTANCE_COUNT));
+      OUT_BATCH(stage_state->prog_offset);
+      OUT_BATCH(0);
+      if (prog_data->base.total_scratch) {
+         OUT_RELOC64(stage_state->scratch_bo,
+                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+                     ffs(prog_data->base.total_scratch) - 11);
+      } else {
+         OUT_BATCH(0);
+         OUT_BATCH(0);
+      }
+      OUT_BATCH(GEN7_HS_INCLUDE_VERTEX_HANDLES |
+                SET_FIELD(prog_data->base.dispatch_grf_start_reg,
+                          GEN7_HS_DISPATCH_START_GRF));
+      OUT_BATCH(0); /* MBZ */
+      ADVANCE_BATCH();
+   } else {
+      BEGIN_BATCH(9);
+      OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2));
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+   }
+   brw->tcs.enabled = active;
 }
 
 const struct brw_tracked_state gen8_hs_state = {
    .dirty = {
       .mesa  = 0,
-      .brw   = BRW_NEW_CONTEXT,
+      .brw   = BRW_NEW_BATCH |
+               BRW_NEW_TCS_PROG_DATA |
+               BRW_NEW_TESS_CTRL_PROGRAM,
    },
    .emit = gen8_upload_hs_state,
 };